/* * This file is part of the coreboot project. * * Copyright 2019 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the * GNU General Public License for more details. */ #include #include #include #include static const struct pad_config gpio_table[] = { /* F3 : MEM_STRAP_3 */ PAD_CFG_GPI(GPP_F3, NONE, PLTRST), /* F10 : MEM_STRAP_2 */ PAD_CFG_GPI(GPP_F10, NONE, PLTRST), /* H19 : MEM_STRAP_0 */ PAD_CFG_GPI(GPP_H19, NONE, PLTRST), /* H22 : MEM_STRAP_1 */ PAD_CFG_GPI(GPP_H22, NONE, PLTRST), }; const struct pad_config *override_gpio_table(size_t *num) { *num = ARRAY_SIZE(gpio_table); return gpio_table; } /* GPIOs configured before ramstage */ static const struct pad_config early_gpio_table[] = { /* F3 : MEM_STRAP_3 */ PAD_CFG_GPI(GPP_F3, NONE, PLTRST), /* F10 : MEM_STRAP_2 */ PAD_CFG_GPI(GPP_F10, NONE, PLTRST), /* H19 : MEM_STRAP_0 */ PAD_CFG_GPI(GPP_H19, NONE, PLTRST), /* H22 : MEM_STRAP_1 */ PAD_CFG_GPI(GPP_H22, NONE, PLTRST), }; const struct pad_config *override_early_gpio_table(size_t *num) { *num = ARRAY_SIZE(early_gpio_table); return early_gpio_table; }