# SPDX-License-Identifier: GPL-2.0-or-later
chip soc/amd/cezanne

	# eSPI Configuration
	register "common_config.espi_config" = "{
		.std_io_decode_bitmap = ESPI_DECODE_IO_0x80_EN | ESPI_DECODE_IO_0X60_0X64_EN,
		.generic_io_range[0] = {
			.base = 0x62,
			/*
			 * Only 0x62 and 0x66 are required. But, this is not supported by
			 * standard IO decodes and there are only 4 generic I/O windows
			 * available. Hence, open a window from 0x62-0x67.
			 */
			.size = 5,
		},
		.generic_io_range[1] = {
			.base = 0x800,   /* EC_HOST_CMD_REGION0 */
			.size = 256,     /* EC_HOST_CMD_REGION_SIZE * 2 */
		},
		.generic_io_range[2] = {
			.base = 0x900,   /* EC_LPC_ADDR_MEMMAP */
			.size = 255,     /* EC_MEMMAP_SIZE */
		},
		.generic_io_range[3] = {
			.base = 0x200,   /* EC_LPC_ADDR_HOST_DATA */
			.size = 8,       /* 0x200 - 0x207 */
		},

		.io_mode = ESPI_IO_MODE_QUAD,
		.op_freq_mhz = ESPI_OP_FREQ_33_MHZ,
		.crc_check_enable = 1,
		.dedicated_alert_pin = 1,
		.periph_ch_en = 1,
		.vw_ch_en = 1,
		.oob_ch_en = 0,
		.flash_ch_en = 0,

		.vw_irq_polarity = ESPI_VW_IRQ_LEVEL_HIGH(1) | ESPI_VW_IRQ_LEVEL_HIGH(12),
	}"

	register "i2c_scl_reset" = "GPIO_I2C0_SCL | GPIO_I2C1_SCL |
					GPIO_I2C2_SCL | GPIO_I2C3_SCL"

	device domain 0 on
		device ref gpp_bridge_0 on end # WLAN
		device ref gpp_bridge_1 on end # SD
		device ref gpp_bridge_2 on end # WWAN
		device ref gpp_bridge_3 on end # NVMe

		device ref gpp_bridge_a on  # Internal GPP Bridge 0 to Bus A
			device ref gfx on end # Internal GPU (GFX)
			device ref xhci_0 on # USB 3.1 (USB0)
				chip drivers/usb/acpi
					device ref xhci_0_root_hub on
						chip drivers/usb/acpi
							register "desc" = ""Right Type-C Port""
							register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
							register "group" = "ACPI_PLD_GROUP(1, 1)"
							device ref usb3_port0 on end
						end
						chip drivers/usb/acpi
							register "desc" = ""Right Type-A Port""
							register "type" = "UPC_TYPE_USB3_A"
							register "group" = "ACPI_PLD_GROUP(1, 2)"
							device ref usb3_port1 on end
						end
						chip drivers/usb/acpi
							register "desc" = ""Right Type-C Port""
							register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
							register "group" = "ACPI_PLD_GROUP(1, 1)"
							device ref usb2_port0 on end
						end
						chip drivers/usb/acpi
							register "desc" = ""Right Type-A Port""
							register "type" = "UPC_TYPE_USB3_A"
							register "group" = "ACPI_PLD_GROUP(1, 2)"
							device ref usb2_port1 on end
						end
						chip drivers/usb/acpi
							register "desc" = ""User-Facing Camera""
							register "type" = "UPC_TYPE_INTERNAL"
							device ref usb2_port2 on end
						end
						chip drivers/usb/acpi
							register "desc" = ""World-Facing Camera""
							register "type" = "UPC_TYPE_INTERNAL"
							device ref usb2_port3 on end
						end
					end
				end
			end
			device ref xhci_1 on # USB 3.1 (USB1)
				chip drivers/usb/acpi
					device ref xhci_1_root_hub on
						chip drivers/usb/acpi
							register "desc" = ""Left Type-C Port""
							register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
							register "group" = "ACPI_PLD_GROUP(2, 2)"
							device ref usb3_port4 on end
						end
						chip drivers/usb/acpi
							register "desc" = ""Left Type-A Port""
							register "type" = "UPC_TYPE_USB3_A"
							register "group" = "ACPI_PLD_GROUP(2, 1)"
							device ref usb3_port5 on end
						end
						chip drivers/usb/acpi
							register "desc" = ""Left Type-C Port""
							register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
							register "group" = "ACPI_PLD_GROUP(2, 2)"
							device ref usb2_port4 on end
						end
						chip drivers/usb/acpi
							register "desc" = ""Left Type-A Port""
							register "type" = "UPC_TYPE_USB3_A"
							register "group" = "ACPI_PLD_GROUP(2, 1)"
							device ref usb2_port5 on end
						end
						chip drivers/usb/acpi
							register "desc" = ""Bluetooth""
							register "type" = "UPC_TYPE_INTERNAL"
							device ref usb2_port6 on end
						end
					end
				end
			end
		end

		device ref lpc_bridge on
			chip ec/google/chromeec
				device pnp 0c09.0 on end
			end
		end
	end # domain
end	# chip soc/amd/cezanne