chip soc/intel/icelake

	# GPE configuration
	# Note that GPE events called out in ASL code rely on this
	# route. i.e. If this route changes then the affected GPE
	# offset bits also need to be changed.
	register "gpe0_dw0" = "PMC_GPP_B"
	register "gpe0_dw1" = "PMC_GPP_D"
	register "gpe0_dw2" = "PMC_GPP_C"

	device cpu_cluster 0 on
		device lapic 0 on end
	end

	register "PchHdaDspEnable" = "1"
	register "PchHdaAudioLinkSsp0" = "1"
	register "PchHdaAudioLinkSsp1" = "1"

	# FSP configuration
	register "SaGv" = "SaGv_Enabled"
	register "SmbusEnable" = "1"
	register "ScsEmmcHs400Enabled" = "1"

	register "usb2_ports[0]" = "USB2_PORT_LONG(OC2)"	# Type-C Port 1
	register "usb2_ports[1]" = "USB2_PORT_LONG(OC2)"	# Type-C Port 2
	register "usb2_ports[2]" = "USB2_PORT_LONG(OC2)"	# Type-C Port 3
	register "usb2_ports[3]" = "USB2_PORT_MID(OC2)"		# Type-A
	register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)"	# Bluetooth
	register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)"	# Camera

	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)"
	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)"
	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)"
	register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC2)"
	register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC2)"
	register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC2)"

	# Enable Pch iSCLK
	register "pch_isclk" = "1"

	# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
	register "gen1_dec" = "0x00fc0801"
	register "gen2_dec" = "0x000c0201"
	# EC memory map range is 0x900-0x9ff
	register "gen3_dec" = "0x00fc0901"

	register "PcieRpEnable[0]" = "1"
	register "PcieRpEnable[1]" = "1"
	register "PcieRpEnable[2]" = "1"
	register "PcieRpEnable[3]" = "1"
	register "PcieRpEnable[4]" = "1"
	register "PcieRpEnable[5]" = "1"
	register "PcieRpEnable[6]" = "1"
	register "PcieRpEnable[7]" = "1"
	register "PcieRpEnable[8]" = "1"
	register "PcieRpEnable[9]" = "1"
	register "PcieRpEnable[10]" = "1"
	register "PcieRpEnable[11]" = "1"
	register "PcieRpEnable[12]" = "1"
	register "PcieRpEnable[13]" = "1"
	register "PcieRpEnable[14]" = "1"
	register "PcieRpEnable[15]" = "1"

	register "PcieClkSrcUsage[0]" = "0x80"
	register "PcieClkSrcUsage[1]" = "7"
	register "PcieClkSrcUsage[2]" = "8"
	register "PcieClkSrcUsage[3]" = "0x80"
	register "PcieClkSrcUsage[4]" = "0x80"
	register "PcieClkSrcUsage[5]" = "0x80"
	register "PcieClkSrcUsage[6]" = "0x80"
	register "PcieClkSrcUsage[7]" = "0x80"
	register "PcieClkSrcUsage[8]" = "0x80"
	register "PcieClkSrcUsage[9]" = "0x80"
	register "PcieClkSrcUsage[10]" = "0x80"
	register "PcieClkSrcUsage[11]" = "0x80"
	register "PcieClkSrcUsage[12]" = "0x80"
	register "PcieClkSrcUsage[13]" = "0x80"
	register "PcieClkSrcUsage[14]" = "0x80"
	register "PcieClkSrcUsage[15]" = "0x80"

	register "PcieClkSrcClkReq[0]" = "0"
	register "PcieClkSrcClkReq[1]" = "1"
	register "PcieClkSrcClkReq[2]" = "2"
	register "PcieClkSrcClkReq[3]" = "3"
	register "PcieClkSrcClkReq[4]" = "4"
	register "PcieClkSrcClkReq[5]" = "5"
	register "PcieClkSrcClkReq[6]" = "6"
	register "PcieClkSrcClkReq[7]" = "7"
	register "PcieClkSrcClkReq[8]" = "8"
	register "PcieClkSrcClkReq[9]" = "9"
	register "PcieClkSrcClkReq[10]" = "10"
	register "PcieClkSrcClkReq[11]" = "11"
	register "PcieClkSrcClkReq[12]" = "12"
	register "PcieClkSrcClkReq[13]" = "13"
	register "PcieClkSrcClkReq[14]" = "14"
	register "PcieClkSrcClkReq[15]" = "15"

	register "SerialIoI2cMode" = "{
		[PchSerialIoIndexI2C0]  = PchSerialIoPci,
		[PchSerialIoIndexI2C1]  = PchSerialIoPci,
		[PchSerialIoIndexI2C2]  = PchSerialIoPci,
		[PchSerialIoIndexI2C3]  = PchSerialIoPci,
		[PchSerialIoIndexI2C4]  = PchSerialIoSkipInit,
		[PchSerialIoIndexI2C5]  = PchSerialIoDisabled,
	}"

	register "SerialIoGSpiMode" = "{
		[PchSerialIoIndexGSPI0] = PchSerialIoPci,
		[PchSerialIoIndexGSPI1] = PchSerialIoPci,
		[PchSerialIoIndexGSPI2] = PchSerialIoDisabled,
	}"

	register "SerialIoGSpiCsMode" = "{
		[PchSerialIoIndexGSPI0] = 1,
		[PchSerialIoIndexGSPI1] = 1,
		[PchSerialIoIndexGSPI2] = 1,
	}"

	register "SerialIoGSpiCsState" = "{
		[PchSerialIoIndexGSPI0] = 0,
		[PchSerialIoIndexGSPI1] = 0,
		[PchSerialIoIndexGSPI2] = 0,
	}"

	register "SerialIoUartMode" = "{
		[PchSerialIoIndexUART0] = PchSerialIoSkipInit,
		[PchSerialIoIndexUART1] = PchSerialIoDisabled,
		[PchSerialIoIndexUART2] = PchSerialIoSkipInit,
	}"

	# Enable "Intel Speed Shift Technology"
	register "speed_shift_enable" = "1"

	# GPIO for SD card detect
	register "sdcard_cd_gpio" = "GPP_G5"

	# Enable S0ix
	register "s0ix_enable" = "0"

	# Intel Common SoC Config
	#+-------------------+---------------------------+
	#| Field             |  Value                    |
	#+-------------------+---------------------------+
	#| chipset_lockdown  | CHIPSET_LOCKDOWN_COREBOOT |
	#| GSPI0             | cr50 TPM. Early init is   |
	#|                   | required to set up a BAR  |
	#|                   | for TPM communication     |
	#|                   | before memory is up       |
	#| pch_thermal_trip  | PCH Trip Temperature      |
	#+-------------------+---------------------------+

	register "common_soc_config" = "{
		.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
		.gspi[0] = {
			.speed_mhz = 1,
			.early_init = 1,
		},
		.i2c[3] = {
			.speed = I2C_SPEED_FAST,
			.speed_config[0] = {
				.speed = I2C_SPEED_FAST,
				.scl_lcnt = 176,
				.scl_hcnt = 95,
				.sda_hold = 36,
			}
		},
		.pch_thermal_trip = 77,
	}"

	# GPIO PM programming
	register "gpio_override_pm" = "1"

	# GPIO community PM configuration
	register "gpio_pm[COMM_0]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG"
	register "gpio_pm[COMM_1]" = "MISCCFG_GPSIDEDPCGEN | MISCCFG_GPRTCDLCGEN | MISCCFG_GSXSLCGEN | MISCCFG_GPDPCGEN | MISCCFG_GPDLCGEN"
	register "gpio_pm[COMM_2]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG"
	register "gpio_pm[COMM_3]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG"
	register "gpio_pm[COMM_4]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG"

	device domain 0 on
		device pci 00.0 on  end # Host Bridge
		device pci 02.0 on  end # Integrated Graphics Device
		device pci 04.0 off  end # SA Thermal device
		device pci 12.0 on  end # Thermal Subsystem
		device pci 12.5 off end # UFS SCS
		device pci 12.6 off end # GSPI #2
		device pci 14.0 on
			chip drivers/usb/acpi
				register "desc" = ""Root Hub""
				register "type" = "UPC_TYPE_HUB"
				device usb 0.0 on
					chip drivers/usb/acpi
						register "desc" = ""USB2 Type-C Right""
						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
						device usb 2.0 on end
					end
					chip drivers/usb/acpi
						register "desc" = ""USB3 Type-C Rear Left""
						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
						device usb 2.1 on end
					end
					chip drivers/usb/acpi
						register "desc" = ""USB3 Type-C Front Left""
						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
						device usb 2.2 on end
					end
					chip drivers/usb/acpi
						register "desc" = ""USB3 Type-A Right""
						register "type" = "UPC_TYPE_USB3_A"
						device usb 2.3 on end
					end
					chip drivers/usb/acpi
						register "desc" = ""USB2 Bluetooth""
						register "type" = "UPC_TYPE_INTERNAL"
						device usb 2.4 on end
					end
					chip drivers/usb/acpi
						register "desc" = ""USB2 Camera""
						register "type" = "UPC_TYPE_INTERNAL"
						device usb 2.5 on end
					end
					chip drivers/usb/acpi
						register "desc" = ""USB3 Type-C Right""
						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
						device usb 3.0 on end
					end
					chip drivers/usb/acpi
						register "desc" = ""USB3 Type-C Rear Left""
						register "type" = "UPC_TYPE_USB3_A"
						device usb 3.1 on end
					end
					chip drivers/usb/acpi
						register "desc" = ""USB3 Type-C Front Right""
						register "type" = "UPC_TYPE_USB3_A"
						device usb 3.2 on end
					end
					chip drivers/usb/acpi
						register "desc" = ""USB3 Type-A Right""
						register "type" = "UPC_TYPE_USB3_A"
						device usb 3.3 on end
					end
				end
			end
		end # USB xHCI
		device pci 14.2 off end # PMC SRAM
		device pci 14.1 off end # USB xDCI (OTG)
		chip drivers/intel/wifi
			register "wake" = "GPE0_PME_B0"
			device pci 14.3 on  end # CNVi wifi
		end
		device pci 14.5 on  end # SDCard
		device pci 15.0 on  end # I2C #0
		device pci 15.1 on
			chip drivers/i2c/generic
				register "hid" = ""ELAN0000""
				register "desc" = ""ELAN Touchpad""
				register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D1_IRQ)"
				register "wake" = "GPE0_DW1_00"
				device i2c 15 on end
			end
		end # I2C #1
		device pci 15.2 on  end # I2C #2
		device pci 15.3 on
				chip drivers/i2c/max98373
				register "vmon_slot_no" = "4"
				register "imon_slot_no" = "5"
				register "uid" = "0"
				register "desc" = ""RIGHT SPEAKER AMP""
				register "name" = ""MAXR""
				device i2c 31 on end
			end
			chip drivers/i2c/max98373
				register "vmon_slot_no" = "6"
				register "imon_slot_no" = "7"
				register "uid" = "1"
				register "desc" = ""LEFT SPEAKER AMP""
				register "name" = ""MAXL""
				device i2c 32 on end
			end
		end # I2C #3
		device pci 16.0 on  end # Management Engine Interface 1
		device pci 16.1 off end # Management Engine Interface 2
		device pci 16.2 off end # Management Engine IDE-R
		device pci 16.3 off end # Management Engine KT Redirection
		device pci 16.4 off end # Management Engine Interface 3
		device pci 16.5 off end # Management Engine Interface 4
		device pci 17.0 off  end # SATA
		device pci 19.0 on  end # I2C #4
		device pci 19.1 off end # I2C #5
		device pci 19.2 on  end # UART #2
		device pci 1a.0 on  end # eMMC
		device pci 1c.0 on
			chip drivers/intel/wifi
				register "wake" = "GPE0_DW0_06"
				device pci 00.0 on end
			end
		end # PCI Express Port 1 x4 SLOT1
		device pci 1c.4 off  end # PCI Express Port 5 x1 SLOT2/LAN
		device pci 1c.5 off end # PCI Express Port 6
		device pci 1c.6 off end # PCI Express Port 7
		device pci 1c.7 off end # PCI Express Port 8
		device pci 1d.0 on  end # PCI Express Port 9
		device pci 1d.1 off end # PCI Express Port 10
		device pci 1d.2 off end # PCI Express Port 11
		device pci 1d.3 off end # PCI Express Port 12
		device pci 1d.4 off end # PCI Express Port 13
		device pci 1d.5 off end # PCI Express Port 14
		device pci 1d.6 off end # PCI Express Port 15
		device pci 1d.7 off end # PCI Express Port 16
		device pci 1e.0 on  end # UART #0
		device pci 1e.1 off end # UART #1
		device pci 1e.2 on
			chip drivers/spi/acpi
				register "hid" = "ACPI_DT_NAMESPACE_HID"
				register "compat_string" = ""google,cr50""
				register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)"
				device spi 0 on end
			end
		end # GSPI #0
		device pci 1e.3 off end # GSPI #1
		device pci 1f.0 on end # LPC Interface
		device pci 1f.1 on  end # P2SB
		device pci 1f.2 on  end # Power Management Controller
		device pci 1f.3 on  end # Intel HDA
		device pci 1f.4 on  end # SMBus
		device pci 1f.5 on  end # PCH SPI
		device pci 1f.6 off end # GbE
	end
end