chip soc/intel/skylake

	# Enable deep Sx states
	register "deep_s3_enable" = "1"
	register "deep_s5_enable" = "1"
	register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN"

	# GPE configuration
	# Note that GPE events called out in ASL code rely on this
	# route. i.e. If this route changes then the affected GPE
	# offset bits also need to be changed.
	register "gpe0_dw0" = "GPP_B"
	register "gpe0_dw1" = "GPP_D"
	register "gpe0_dw2" = "GPP_E"

	# EC host command range is in 0x800-0x8ff
	register "gen1_dec" = "0x00fc0801"

	# Enable DPTF
	register "dptf_enable" = "1"

	# FSP Configuration
	register "ProbelessTrace" = "0"
	register "EnableLan" = "0"
	register "EnableSata" = "0"
	register "SataSalpSupport" = "0"
	register "SataMode" = "0"
	register "SataPortsEnable[0]" = "0"
	register "EnableAzalia" = "1"
	register "DspEnable" = "1"
	register "IoBufferOwnership" = "3"
	register "EnableTraceHub" = "0"
	register "XdciEnable" = "0"
	register "SsicPortEnable" = "0"
	register "SmbusEnable" = "1"
	register "Cio2Enable" = "0"
	register "ScsEmmcEnabled" = "1"
	register "ScsEmmcHs400Enabled" = "1"
	register "ScsSdCardEnabled" = "2"
	register "IshEnable" = "0"
	register "PttSwitch" = "0"
	register "InternalGfx" = "1"
	register "SkipExtGfxScan" = "1"
	register "Device4Enable" = "1"

	# Enable Root port 1 and 5.
	register "PcieRpEnable[0]" = "1"
	register "PcieRpEnable[4]" = "1"
	# Enable CLKREQ#
	register "PcieRpClkReqSupport[0]" = "1"
	register "PcieRpClkReqSupport[4]" = "1"
	# RP 1 uses SRCCLKREQ1# while RP 5 uses SRCCLKREQ2#
	register "PcieRpClkReqNumber[0]" = "1"
	register "PcieRpClkReqNumber[4]" = "2"

	register "PortUsb20Enable[0]" = "1"	# Type-C Port 1
	register "PortUsb20Enable[1]" = "1"	# Type-A Port
	register "PortUsb20Enable[2]" = "1"	# Camera
	register "PortUsb20Enable[3]" = "1"	# Bluetooth
	register "PortUsb20Enable[4]" = "1"	# SD
	register "PortUsb20Enable[5]" = "1"	# Type-C Port 2

	register "PortUsb30Enable[0]" = "1"	# Type-C Port 1
	register "PortUsb30Enable[1]" = "1"	# Type-C Port 2
	register "PortUsb30Enable[2]" = "1"	# Type-A Port
	register "PortUsb30Enable[3]" = "1"	# SD

	# USB Per Port HS Preemphasis Bias
	register "Usb2AfePetxiset" = "{ 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, \
					0x07, 0x07, 0x07, 0x07, 0x07, 0x07, \
					0x07, 0x07, 0x07, 0x07 }"

	# USB Per Port HS Transmitter Bias
	register "Usb2AfeTxiset" = "{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
				      0x00, 0x00, 0x05, 0x00, 0x00, 0x00, \
				      0x00, 0x00, 0x00, 0x00 }"

	# USB Per Port HS Transmitter Emphasis
	register "Usb2AfePredeemp" = "{ 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, \
					0x02, 0x02, 0x02, 0x02, 0x03, 0x03, \
					0x03, 0x03, 0x03, 0x03 }"

	# USB Per Port Half Bit Pre-emphasis
	register "Usb2AfePehalfbit" = "{ 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, \
					 0x01, 0x01, 0x01, 0x01, 0x00, 0x00, \
					 0x00, 0x00, 0x00, 0x00 }"

	# Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment
	register "Usb3HsioTxDeEmphEnable" = "{ 0x00, 0x00, 0x00, 0x00, 0x00, \
					       0x00, 0x00, 0x00, 0x00, 0x00 }"

	# USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting
	register "Usb3HsioTxDeEmph" = "{ 0x00, 0x00, 0x00, 0x00, 0x00, \
					 0x00, 0x00, 0x00, 0x00, 0x00 }"

	# Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment
	register "Usb3HsioTxDownscaleAmpEnable" = "{ 0x00, 0x00, 0x00, 0x00, \
						     0x00, 0x00, 0x00, 0x00, \
						     0x00, 0x00 }"

	# USB 3.0 TX Output Downscale Amplitude Adjustment
	register "Usb3HsioTxDownscaleAmp" = "{ 0x00, 0x00, 0x00, 0x00, 0x00, \
					       0x00, 0x00, 0x00, 0x00, 0x00 }"

	# Must leave UART0 enabled or SD/eMMC will not work as PCI
	register "SerialIoDevMode" = "{ \
		[PchSerialIoIndexI2C0]  = PchSerialIoPci, \
		[PchSerialIoIndexI2C1]  = PchSerialIoPci, \
		[PchSerialIoIndexI2C2]  = PchSerialIoDisabled, \
		[PchSerialIoIndexI2C3]  = PchSerialIoDisabled, \
		[PchSerialIoIndexI2C4]  = PchSerialIoPci, \
		[PchSerialIoIndexI2C5]  = PchSerialIoDisabled, \
		[PchSerialIoIndexSpi0]  = PchSerialIoDisabled, \
		[PchSerialIoIndexSpi1]  = PchSerialIoDisabled, \
		[PchSerialIoIndexUart0] = PchSerialIoPci, \
		[PchSerialIoIndexUart1] = PchSerialIoDisabled, \
		[PchSerialIoIndexUart2] = PchSerialIoSkipInit, \
	}"

	device cpu_cluster 0 on
		device lapic 0 on end
	end
	device domain 0 on
		device pci 00.0 on  end # Host Bridge
		device pci 02.0 on  end # Integrated Graphics Device
		device pci 14.0 on  end # USB xHCI
		device pci 14.1 off end # USB xDCI (OTG)
		device pci 14.2 on  end # Thermal Subsystem
		device pci 15.0 on  end # I2C #0
		device pci 15.1 on  end # I2C #1
		device pci 15.2 off end # I2C #2
		device pci 15.3 off end # I2C #3
		device pci 16.0 on  end # Management Engine Interface 1
		device pci 16.1 off end # Management Engine Interface 2
		device pci 16.2 off end # Management Engine IDE-R
		device pci 16.3 off end # Management Engine KT Redirection
		device pci 16.4 off end # Management Engine Interface 3
		device pci 17.0 off end # SATA
		device pci 19.0 on  end # UART #2
		device pci 19.1 off end # I2C #5
		device pci 19.2 on  end # I2C #4
		device pci 1c.0 on  end # PCI Express Port 1
		device pci 1c.1 off end # PCI Express Port 2
		device pci 1c.2 off end # PCI Express Port 3
		device pci 1c.3 off end # PCI Express Port 4
		device pci 1c.4 on  end # PCI Express Port 5
		device pci 1c.5 off end # PCI Express Port 6
		device pci 1c.6 off end # PCI Express Port 7
		device pci 1c.7 off end # PCI Express Port 8
		device pci 1d.0 off end # PCI Express Port 9
		device pci 1d.1 off end # PCI Express Port 10
		device pci 1d.2 off end # PCI Express Port 11
		device pci 1d.3 off end # PCI Express Port 12
		device pci 1e.0 on  end # UART #0
		device pci 1e.1 off end # UART #1
		device pci 1e.2 off end # GSPI #0
		device pci 1e.3 off end # GSPI #1
		device pci 1e.4 on  end # eMMC
		device pci 1e.5 off end # SDIO
		device pci 1e.6 on  end # SDCard
		device pci 1f.0 on
			chip drivers/pc80/tpm
				device pnp 0c31.0 on end
			end
			chip ec/google/chromeec
				device pnp 0c09.0 on end
			end
		end # LPC Interface
		device pci 1f.2 on  end # Power Management Controller
		device pci 1f.3 on  end # Intel HDA
		device pci 1f.4 on  end # SMBus
		device pci 1f.5 on  end # PCH SPI
		device pci 1f.6 off end # GbE
	end
end