/* SPDX-License-Identifier: GPL-2.0-only */ #include #include #include #include #include #include #include void mainboard_late_rcba_config(void) { /* * GFX INTA -> PIRQA (MSI) * D28IP_P1IP WLAN INTA -> PIRQB * D28IP_P2IP ETH0 INTB -> PIRQF * D28IP_P3IP SDCARD INTC -> PIRQD * D29IP_E1P EHCI1 INTA -> PIRQD * D26IP_E2P EHCI2 INTA -> PIRQF * D31IP_SIP SATA INTA -> PIRQB (MSI) * D31IP_SMIP SMBUS INTB -> PIRQH * D31IP_TTIP THRT INTC -> PIRQA * D27IP_ZIP HDA INTA -> PIRQA (MSI) * * Trackpad interrupt is edge triggered and cannot be shared. * TRACKPAD -> PIRQG */ /* Device interrupt pin register (board specific) */ RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); RCBA32(D29IP) = (INTA << D29IP_E1P); RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTB << D28IP_P2IP) | (INTC << D28IP_P3IP); RCBA32(D27IP) = (INTA << D27IP_ZIP); RCBA32(D26IP) = (INTA << D26IP_E2P); RCBA32(D25IP) = (NOINT << D25IP_LIP); RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); /* Device interrupt route registers */ DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC); DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG); DIR_ROUTE(D28IR, PIRQB, PIRQF, PIRQD, PIRQE); DIR_ROUTE(D27IR, PIRQA, PIRQH, PIRQA, PIRQB); DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH); DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); } const struct southbridge_usb_port mainboard_usb_ports[] = { /* enabled power USB oc pin */ { 1, 0, -1 }, /* P0: Right USB 3.0 #1 (no OC) */ { 1, 0, -1 }, /* P1: Right USB 3.0 #2 (no OC) */ { 1, 0, -1 }, /* P2: Camera (no OC) */ { 0, 0, -1 }, /* P3: Empty */ { 0, 0, -1 }, /* P4: Empty */ { 0, 0, -1 }, /* P5: Empty */ { 0, 0, -1 }, /* P6: Empty */ { 0, 0, -1 }, /* P7: Empty */ { 0, 0, -1 }, /* P8: Empty */ { 1, 1, -1 }, /* P9: Left USB 1 (no OC) */ { 1, 0, -1 }, /* P10: Mini PCIe - WLAN / BT (no OC) */ { 0, 0, -1 }, /* P11: Empty */ { 0, 0, -1 }, /* P12: Empty */ { 0, 0, -1 }, /* P13: Empty */ }; void mainboard_get_spd(spd_raw_data *spd, bool id_only) { read_spd(&spd[0], 0x50, id_only); read_spd(&spd[2], 0x52, id_only); } void mainboard_fill_pei_data(struct pei_data *pei_data) { const uint8_t spdaddr[] = {0xA0, 0x00, 0xA4, 0x00}; memcpy(pei_data->spd_addresses, &spdaddr, sizeof(pei_data->spd_addresses)); /* TODO: Confirm if nortbridge_fill_pei_data() gets .system_type right (should be 0) */ }