chip soc/intel/alderlake
	#+-------------------+---------------------------+
	#| Field             |  Value                    |
	#+-------------------+---------------------------+
	#| GSPI1             | FPMCU                     |
	#| I2C0              | Audio                     |
	#| I2C1              | cr50 TPM. Early init is   |
	#|                   | required to set up a BAR  |
	#|                   | for TPM communication     |
	#| I2C2              | Misc (Cam, Display, LED)  |
	#| I2C3              | Touchscreen               |
	#| I2C4              | NC                        |
	#| I2C5              | Touchpad                  |
	#+-------------------+---------------------------+
	register "common_soc_config" = "{
		.i2c[0] = {
			.speed = I2C_SPEED_STANDARD,
			.speed_config[0] = {
				.speed = I2C_SPEED_STANDARD,
				.scl_lcnt = 45,
				.scl_hcnt = 33,
				.sda_hold = 20,
			},
		},
		.i2c[1] = {
			.early_init = 1,
			.speed = I2C_SPEED_STANDARD,
			.rise_time_ns = 600,
			.fall_time_ns = 400,
			.data_hold_time_ns = 50,
		},
		.i2c[2] = {
			.speed = I2C_SPEED_STANDARD,
			.rise_time_ns = 650,
			.fall_time_ns = 400,
			.data_hold_time_ns = 50,
		},
		.i2c[3] = {
			.speed = I2C_SPEED_STANDARD,
			.rise_time_ns = 650,
			.fall_time_ns = 400,
			.data_hold_time_ns = 50,
		},
		.i2c[5] = {
			.speed = I2C_SPEED_STANDARD,
			.rise_time_ns = 650,
			.fall_time_ns = 400,
			.data_hold_time_ns = 50,
		},
	}"

	# I2C Port Config
	register "serial_io_i2c_mode" = "{
		[PchSerialIoIndexI2C0] = PchSerialIoPci,
		[PchSerialIoIndexI2C1] = PchSerialIoPci,
		[PchSerialIoIndexI2C2] = PchSerialIoPci,
		[PchSerialIoIndexI2C3] = PchSerialIoPci,
		[PchSerialIoIndexI2C4] = PchSerialIoDisabled,
		[PchSerialIoIndexI2C5] = PchSerialIoPci,
		[PchSerialIoIndexI2C7] = PchSerialIoDisabled,
	}"
	device domain 0 on
		device ref pcie4_0 on
			# Enable CPU PCIE RP 1 using CLK 1
			register "cpu_pcie_rp[CPU_RP(1)]" = "{
				.clk_req = 1,
				.clk_src = 1,
				.flags = PCIE_RP_LTR | PCIE_RP_AER,
			}"
		end
		device ref tbt_pcie_rp3 on end
		device ref cnvi_wifi on
			chip drivers/wifi/generic
				register "wake" = "GPE0_PME_B0"
				device generic 0 on end
			end
		end
		device ref pcie_rp6 off end
		device ref pcie_rp7 off end
		device ref pcie_rp8 off end
		device ref pcie_rp9 on
			# Enable NVMe on PCIE 9-12 using clk 1
			register "pch_pcie_rp[PCH_RP(9)]" = "{
				.clk_src = 1,
				.clk_req = 0,
				.flags = PCIE_RP_LTR | PCIE_RP_AER,
			}"
		end
		device ref tcss_dma0 on
			chip drivers/intel/usb4/retimer
				register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)"
				use tcss_usb3_port1 as dfp[0].typec_port
				device generic 0 on end
			end
		end
		device ref tcss_dma1 on
			chip drivers/intel/usb4/retimer
				register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)"
				use tcss_usb3_port3 as dfp[0].typec_port
				device generic 0 on end
			end
		end
		device ref i2c1 on
			chip drivers/i2c/tpm
				register "hid" = ""GOOG0005""
				register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)"
				device i2c 50 on end
			end
		end
		device ref gspi1 on
			chip drivers/spi/acpi
				register "name" = ""CRFP""
				register "hid" = "ACPI_DT_NAMESPACE_HID"
				register "uid" = "1"
				register "compat_string" = ""google,cros-ec-spi""
				register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F15_IRQ)"
				register "wake" = "GPE0_DW2_15"
				device spi 0 on end
			end # FPMCU
		end
		device ref pch_espi on
			chip ec/google/chromeec
				# Replicate Brya, except we have 2 ports instead of 3.
				use conn0 as mux_conn[0]
				use conn1 as mux_conn[1]
				device pnp 0c09.0 on end
			end
		end
		device ref pmc hidden
			chip drivers/intel/pmc_mux
				device generic 0 on
					chip drivers/intel/pmc_mux/conn
						use usb2_port1 as usb2_port
						use tcss_usb3_port3 as usb3_port
						device generic 0 alias conn0 on end
					end
					chip drivers/intel/pmc_mux/conn
						use usb2_port2 as usb2_port
						use tcss_usb3_port2 as usb3_port
						device generic 1 alias conn1 on end
					end
				end
			end
		end
		device ref tcss_xhci on
			chip drivers/usb/acpi
				device ref tcss_root_hub on
					chip drivers/usb/acpi
						register "desc" = ""USB3 Type-C Port C0 (DB)""
						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
						register "use_custom_pld" = "true"
						# USB C0 is on RIGHT panel, LEFT side (when user is facing front)
						register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(1, 1))"
						device ref tcss_usb3_port3 on end
					end
					chip drivers/usb/acpi
						register "desc" = ""USB3 Type-C Port C1 (MLB)""
						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
						register "use_custom_pld" = "true"
						# USB C1 is on the RIGHT panel, RIGHT side (when user is facing front)
						register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))"
						device ref tcss_usb3_port2 on end
					end
				end
			end
		end
		device ref xhci on
			chip drivers/usb/acpi
				device ref xhci_root_hub on
					chip drivers/usb/acpi
						register "desc" = ""USB2 Type-C Port C0 (DB)""
						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
						register "use_custom_pld" = "true"
						register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(1, 1))"
						device ref usb2_port1 on end
					end
					chip drivers/usb/acpi
						register "desc" = ""USB2 Type-C Port C1 (MLB)""
						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
						register "use_custom_pld" = "true"
						register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))"
						device ref usb2_port2 on end
					end
				end
			end
		end
	end
end