chip soc/intel/alderlake
	device cpu_cluster 0 on
		device lapic 0 on end
	end

	# GPE configuration
	register "pmc_gpe0_dw0" = "GPP_A"
	register "pmc_gpe0_dw1" = "GPP_E"
	register "pmc_gpe0_dw2" = "GPP_F"

	# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
	register "gen1_dec" = "0x00fc0801"
	register "gen2_dec" = "0x000c0201"
	# EC memory map range is 0x900-0x9ff
	register "gen3_dec" = "0x00fc0901"

        # S0ix enable
        register "s0ix_enable" = "1"

	# DPTF enable
	register "dptf_enable" = "1"

	register "power_limits_config" = "{
		.tdp_pl1_override = 15,
		.tdp_pl2_override = 55,
	}"

	# Enable heci communication
	register "HeciEnabled" = "1"

	# This disabled autonomous GPIO power management, otherwise
	# old cr50 FW only supports short pulses; need to clarify
	# the minimum PCH IRQ pulse width with Intel, b/180111628
	register "gpio_override_pm" = "1"
	register "gpio_pm[COMM_0]" = "0"
	register "gpio_pm[COMM_1]" = "0"
	register "gpio_pm[COMM_2]" = "0"
	register "gpio_pm[COMM_4]" = "0"
	register "gpio_pm[COMM_5]" = "0"

	# Enable CNVi BT
	register "CnviBtCore" = "true"

	register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)"	# USB2_C0
	register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC1)"	# USB2_C1
	register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC2)"	# USB2_C2
	register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)"	# M.2 WWAN
	register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)"	# M.2 Camera
	register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)"	# Type-A Port A0
	register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)"	# M.2 Bluetooth

	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC3)"	# USB3/2 Type A port A0
	# TODO(b/184324979): Workaround to enable TCSS ports. FSP v2081
	# uses port enable for south XHCI ports to determine if TCSS
	# ports should be enabled. Until FSP is fixed, enable south
	# XHCI ports 1 and 2.
	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)"
	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)"
	register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# M.2 WWAN

	register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC0)"
	register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC1)"
	register "tcss_ports[2]" = "TCSS_PORT_DEFAULT(OC2)"

	register "SerialIoI2cMode" = "{
		[PchSerialIoIndexI2C0] = PchSerialIoPci,
		[PchSerialIoIndexI2C1] = PchSerialIoPci,
		[PchSerialIoIndexI2C2] = PchSerialIoPci,
		[PchSerialIoIndexI2C3] = PchSerialIoPci,
		[PchSerialIoIndexI2C4] = PchSerialIoPci,
		[PchSerialIoIndexI2C5] = PchSerialIoPci,
	}"

	register "SerialIoGSpiMode" = "{
		[PchSerialIoIndexGSPI0] = PchSerialIoDisabled,
		[PchSerialIoIndexGSPI1] = PchSerialIoPci,
	}"

	register "SerialIoUartMode" = "{
		[PchSerialIoIndexUART0] = PchSerialIoPci,
		[PchSerialIoIndexUART1] = PchSerialIoDisabled,
		[PchSerialIoIndexUART2] = PchSerialIoDisabled,
	}"

	# HD Audio
	register "PchHdaDspEnable" = "1"
	register "PchHdaIDispLinkTmode" = "HDA_TMODE_8T"
	register "PchHdaIDispLinkFrequency" = "HDA_LINKFREQ_96MHZ"
	register "PchHdaIDispCodecEnable" = "1"

	# Intel Common SoC Config
	#+-------------------+---------------------------+
	#| Field             |  Value                    |
	#+-------------------+---------------------------+
	#| chipset_lockdown  | CHIPSET_LOCKDOWN_COREBOOT |
	#| GSPI1             | Fingerprint MCU           |
	#| I2C0              | Audio                     |
	#| I2C1              | Touchscreen               |
	#| I2C2              | SAR0                      |
	#| I2C3              | cr50 TPM. Early init is   |
	#|                   | required to set up a BAR  |
	#|                   | for TPM communication     |
	#| I2C4              | CAM                       |
	#| I2C5              | Trackpad                  |
	#+-------------------+---------------------------+
	register "common_soc_config" = "{
		.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
		.i2c[0] = {
			.speed = I2C_SPEED_FAST,
		},
		.i2c[1] = {
			.speed = I2C_SPEED_FAST,
		},
		.i2c[2] = {
			.speed = I2C_SPEED_FAST,
		},
		.i2c[3] = {
			.early_init = 1,
			.speed = I2C_SPEED_FAST,
		},
		.i2c[4] = {
			.speed = I2C_SPEED_FAST,
		},
		.i2c[5] = {
			.speed = I2C_SPEED_FAST,
		},
	}"

	device domain 0 on
		device ref igpu on end
		device ref dtt on end
		device ref ipu on end
		device ref tbt_pcie_rp0 on end
		device ref tbt_pcie_rp1 on end
		device ref tbt_pcie_rp2 on end
		device ref tcss_xhci on end
		device ref tcss_dma0 on end
		device ref tcss_dma1 on end
		device ref xhci on end
		device ref shared_sram on end
		device ref cnvi_wifi on
			chip drivers/wifi/generic
				register "wake" = "GPE0_PME_B0"
				device generic 0 on end
			end
		end
		device ref i2c3 on
			chip drivers/i2c/tpm
				register "hid" = ""GOOG0005""
				register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)"
				device i2c 50 on end
			end
		end
		device ref heci1 on end
		device ref sata on end
		device ref pcie_rp6 on
			# Enable WWAN PCIE 6 using clk 5
			register "pch_pcie_rp[PCH_RP(6)]" = "{
				.clk_src = 5,
				.clk_req = 5,
				.flags = PCIE_RP_LTR | PCIE_RP_AER,
			}"
		end	#PCIE6 WWAN
		device ref pcie_rp8 on
			# Enable SD Card PCIE 8 using clk 3
			register "pch_pcie_rp[PCH_RP(8)]" = "{
				.clk_src = 3,
				.clk_req = 3,
				.flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER,
			}"
		end	#PCIE8 SD card
		device ref pcie_rp9 on
			# Enable NVMe PCIE 9 using clk 1
			register "pch_pcie_rp[PCH_RP(9)]" = "{
				.clk_src = 1,
				.clk_req = 1,
				.flags = PCIE_RP_LTR | PCIE_RP_AER,
			}"
		end	#PCIE9-12 SSD
		device ref uart0 on end
		device ref gspi1 on end
		device ref pch_espi on
			chip ec/google/chromeec
				device pnp 0c09.0 on end
			end
		end
		device ref hda on end
	end
end