chip soc/intel/alderlake
	device cpu_cluster 0 on
		device lapic 0 on end
	end

	register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)"	# USB2_C0
	register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC1)"	# USB2_C1
	register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC2)"	# USB2_C2
	register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)"	# M.2 WWAN
	register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)"	# M.2 Camera
	register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)"	# Type-A Port A0
	register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)"	# M.2 Bluetooth

	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC3)"	# USB3/2 Type A port A0
	register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# M.2 WWAN

	# Enable WLAN PCIE 5 using clk 2
	register "PchPcieRpEnable[5]" = "1"
	register "PcieRpLtrEnable[5]" = "1"
	register "PcieClkSrcUsage[2]" = "5"
	register "PcieClkSrcClkReq[2]" = "2"
	register "PcieRpAdvancedErrorReporting[5]" = "1"

	# Enable WWAN PCIE 6 using clk 5
	register "PchPcieRpEnable[6]" = "1"
	register "PcieRpLtrEnable[6]" = "1"
	register "PcieClkSrcUsage[5]" = "6"
	register "PcieClkSrcClkReq[5]" = "5"
	register "PcieRpAdvancedErrorReporting[6]" = "1"

	# Enable SD Card PCIE 8 using clk 3
	register "PchPcieRpEnable[7]" = "1"
	register "PcieRpLtrEnable[7]" = "1"
	register "PcieRpHotPlug[7]" = "1"
	register "PcieClkSrcUsage[3]" = "7"
	register "PcieClkSrcClkReq[3]" = "3"
	register "PcieRpAdvancedErrorReporting[7]" = "1"

	# Enable NVMe PCIE 9 using clk 1
	register "PchPcieRpEnable[8]" = "1"
	register "PcieRpLtrEnable[8]" = "1"
	register "PcieClkSrcUsage[1]" = "8"
	register "PcieClkSrcClkReq[1]" = "1"
	register "PcieRpAdvancedErrorReporting[8]" = "1"

	register "SerialIoI2cMode" = "{
		[PchSerialIoIndexI2C0]  = PchSerialIoPci,
		[PchSerialIoIndexI2C1]  = PchSerialIoPci,
		[PchSerialIoIndexI2C2]  = PchSerialIoPci,
		[PchSerialIoIndexI2C3]  = PchSerialIoPci,
		[PchSerialIoIndexI2C4]  = PchSerialIoPci,
		[PchSerialIoIndexI2C5]  = PchSerialIoPci,
	}"

	register "SerialIoGSpiMode" = "{
		[PchSerialIoIndexGSPI0] = PchSerialIoDisabled,
		[PchSerialIoIndexGSPI1] = PchSerialIoPci,
	}"

	register "SerialIoUartMode" = "{
		[PchSerialIoIndexUART0] = PchSerialIoPci,
		[PchSerialIoIndexUART1] = PchSerialIoDisabled,
		[PchSerialIoIndexUART2] = PchSerialIoDisabled,
	}"

	# Intel Common SoC Config
	#+-------------------+---------------------------+
	#| Field             |  Value                    |
	#+-------------------+---------------------------+
	#| chipset_lockdown  | CHIPSET_LOCKDOWN_COREBOOT |
	#| GSPI1             | Fingerprint MCU           |
	#| I2C0              | Audio                     |
	#| I2C1              | Touchscreen               |
	#| I2C2              | SAR0                      |
	#| I2C3              | cr50 TPM. Early init is   |
	#|                   | required to set up a BAR  |
	#|                   | for TPM communication     |
	#| I2C4              | CAM                       |
	#| I2C5              | Trackpad                  |
	#+-------------------+---------------------------+
	register "common_soc_config" = "{
		.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
		.i2c[0] = {
			.speed = I2C_SPEED_FAST,
		},
		.i2c[1] = {
			.speed = I2C_SPEED_FAST,
		},
		.i2c[2] = {
			.speed = I2C_SPEED_FAST,
		},
		.i2c[3] = {
			.early_init = 1,
			.speed = I2C_SPEED_FAST,
		},
		.i2c[4] = {
			.speed = I2C_SPEED_FAST,
		},
		.i2c[5] = {
			.speed = I2C_SPEED_FAST,
		},
	}"

	device domain 0 on
		device ref igpu on end
		device ref dtt on end
		device ref tbt_pcie_rp0 on end
		device ref tbt_pcie_rp1 on end
		device ref tbt_pcie_rp2 on end
		device ref tcss_xhci on end
		device ref tcss_dma0 on end
		device ref tcss_dma1 on end
		device ref cnvi_bt on end
		device ref xhci on end
		device ref shared_sram on end
		device ref cnvi_wifi on
			chip drivers/wifi/generic
				register "wake" = "GPE0_PME_B0"
				device generic 0 on end
			end
		end
		device ref heci1 on end
		device ref sata on end
		device ref pcie_rp5 on end	#PCIE5 WLAN
		device ref pcie_rp6 on end	#PCIE6 WWAN
		device ref pcie_rp8 on end	#PCIE8 SD card
		device ref pcie_rp9 on end	#PCIE9-12 SSD
		device ref uart0 on end
		device ref gspi1 on end
		device ref pch_espi on
			chip ec/google/chromeec
				device pnp 0c09.0 on end
			end
		end
		device ref hda on end
	end
end