fw_config
	field  USBC0_RETIMER	2	3
		option	USBC0_RETIMER_ABSENT	0
		option	USBC0_RETIMER_PRESENT	1
	end
	field  STORAGE  4	5
		option	STORAGE_UNKNOWN	0
		option	STORAGE_NVME	1
		option	STORAGE_EMMC	2
	end
	field AUDIO 6
		option AUDIO_UNKNOWN	0
		option NAU88L25B_I2S	1
	end
end
chip soc/intel/alderlake
	# As per Intel Advisory doc#723158, the change is required to prevent possible
	# display flickering issue.
	register "usb2_phy_sus_pg_disable" = "1"
	# Enable HDMI2 in PortA, HDMI1 in PortB, HDMI/DP in Port2
	register "ddi_ports_config" = "{
		[DDI_PORT_A] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
		[DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
		[DDI_PORT_1] = DDI_ENABLE_HPD,
		[DDI_PORT_2] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
		[DDI_PORT_3] = DDI_ENABLE_HPD,
	}"
	register "usb2_ports[1]" = "USB2_PORT_EMPTY" 		# Disable USB2 Port2
	register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC2)"  	# USB2 Port3
	register "usb2_ports[3]" = "USB2_PORT_SHORT(OC_SKIP)"	# Enable USB2 Port4
	register "usb2_ports[8]" = "USB2_PORT_EMPTY"		# Disable USB2 Port9
	register "usb3_ports[2]" = "{
		.enable           = 1,
		.ocpin            = OC_SKIP,
		.tx_de_emp        = 0x2B,
		.tx_downscale_amp = 0x00,
	}" # Type-A port A2
	register "tcss_ports[3]" = "TCSS_PORT_EMPTY"		# Disable TCP3
	register "tcc_offset" = "0"	# TCC of 100C
	register "power_limits_config[ADL_P_142_242_282_15W_CORE]" = "{
		.tdp_pl1_override = 15,
		.tdp_pl2_override = 25,
	}"
	register "power_limits_config[ADL_P_282_482_28W_CORE]" = "{
		.tdp_pl1_override = 64,
	}"
	device domain 0 on
		device ref dtt on
			chip drivers/intel/dptf
				## sensor information
				register "options.tsr[0].desc" = ""SSD""
				register "options.tsr[1].desc" = ""CPU_VR""
				register "options.tsr[2].desc" = ""DIMM""


				## Passive Policy
				register "policies.passive" = "{
					[0] = DPTF_PASSIVE(CPU,		CPU,           95, 5000),
					[1] = DPTF_PASSIVE(CPU,		TEMP_SENSOR_0, 75, 5000),
					[2] = DPTF_PASSIVE(CPU,		TEMP_SENSOR_1, 75, 5000),
					[3] = DPTF_PASSIVE(CPU,		TEMP_SENSOR_2, 75, 5000),
				}"

				## Critical Policy
				register "policies.critical" = "{
					[0] = DPTF_CRITICAL(CPU,               105, SHUTDOWN),
					[1] = DPTF_CRITICAL(TEMP_SENSOR_0,      85, SHUTDOWN),
					[2] = DPTF_CRITICAL(TEMP_SENSOR_1,      85, SHUTDOWN),
					[3] = DPTF_CRITICAL(TEMP_SENSOR_2,      85, SHUTDOWN),
				}"

				register "controls.power_limits" = "{
					.pl1 = {
							.min_power = 15000,
							.max_power = 55000,
							.time_window_min = 28 * MSECS_PER_SEC,
							.time_window_max = 32 * MSECS_PER_SEC,
							.granularity = 200,
						},
					.pl2 = {
							.min_power = 55000,
							.max_power = 55000,
							.time_window_min = 28 * MSECS_PER_SEC,
							.time_window_max = 32 * MSECS_PER_SEC,
							.granularity = 1000,
						}
				}"

				register "oem_data.oem_variables" = "{
						[0] = 0x1
				}"

				device generic 0 alias dptf_policy on end
			end
		end
		device ref tcss_dma0 on
			chip drivers/intel/usb4/retimer
				register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)"
				use tcss_usb3_port1 as dfp[0].typec_port
				device generic 0 on end
			end
		end
		device ref tcss_dma1 on
			chip drivers/intel/usb4/retimer
				register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)"
				use tcss_usb3_port3 as dfp[0].typec_port
				device generic 0 on end
			end
		end # USB4 Port
		device ref pcie4_0 on
		# Enable CPU PCIE RP 1 using CLK 0
			register "cpu_pcie_rp[CPU_RP(1)]" = "{
				.clk_req = 0,
				.clk_src = 0,
				.flags = PCIE_RP_LTR | PCIE_RP_AER,
			}"
			probe STORAGE STORAGE_NVME
			probe STORAGE STORAGE_UNKNOWN
		end # SSD
		device ref cnvi_wifi on
			chip drivers/wifi/generic
				register "wake" = "GPE0_PME_B0"
				device generic 0 on end
			end
		end # WiFi
		device ref i2c0 on
			chip drivers/i2c/nau8825
				register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A23)"
				register "jkdet_enable" = "1"
				register "jkdet_pull_enable" = "0"
				register "jkdet_pull_up" = "0"
				register "jkdet_polarity" = "1"      # ActiveLow
				register "vref_impedance" = "2"      # 125kOhm
				register "micbias_voltage" = "6"     # 2.754
				register "sar_threshold_num" = "4"
				register "sar_threshold[0]" = "0x0C"
				register "sar_threshold[1]" = "0x1C"
				register "sar_threshold[2]" = "0x38"
				register "sar_threshold[3]" = "0x60"
				register "sar_hysteresis" = "1"
				register "sar_voltage" = "6"
				register "sar_compare_time" = "0"     # 500ns
				register "sar_sampling_time" = "0"    # 2us
				register "short_key_debounce" = "2"   # 100ms
				register "jack_insert_debounce" = "7" # 512ms
				register "jack_eject_debounce" = "7"  # 512ms
				device i2c 1a on end
			end
		end # Audio Nau8825
		device ref pcie_rp6 on
			# Enable PCIe-to-i225 bridge PCIe 6 using clk 4
			register "pch_pcie_rp[PCH_RP(6)]" = "{
				.clk_src = 4,
				.clk_req = 4,
				.flags = PCIE_RP_LTR | PCIE_RP_AER,
			}"
			device pci 00.0 on end
		end # IntelI225V Ethernet NIC
		device ref pcie_rp7 on
			chip drivers/net
				register "customized_leds" = "0x0482"
				register "wake" = "GPE0_DW0_07"
				register "device_index" = "0"
				register "add_acpi_dma_property" = "true"
				device pci 00.0 on end
			end
		end # RTL8111K Ethernet NIC
		device ref pcie_rp8  off end        #pcie_rp    8  Empty
		device ref pcie_rp9  off end        #pcie_rp    9  Empty
		device ref pcie_rp10 off end        #pcie_rp   10  Empty
		device ref pcie_rp11 off end        #pcie_rp   11  Empty
		device ref pcie_rp12 on
			chip soc/intel/common/block/pcie/rtd3
				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A21)"
				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B3)"
				register "srcclk_pin" = "1"
				register "reset_delay_ms" = "50"
				register "enable_delay_ms" = "20"
				device generic 0 on
					probe STORAGE STORAGE_EMMC
					probe STORAGE STORAGE_UNKNOWN
				end
			end # Enable PCIe-to-eMMC bridge PCIE 12 using clk 1
			register "pch_pcie_rp[PCH_RP(12)]" = "{
				.clk_src = 1,
				.clk_req = 1,
				.flags = PCIE_RP_LTR | PCIE_RP_AER,
			}"
			probe STORAGE STORAGE_EMMC
			probe STORAGE STORAGE_UNKNOWN
		end # BH799BB
		device ref pch_espi on
			chip ec/google/chromeec
				use conn0 as mux_conn[0]
				use conn1 as mux_conn[1]
				device pnp 0c09.0 on end
			end
		end
		device ref pmc hidden
			chip drivers/intel/pmc_mux
				device generic 0 on
					chip drivers/intel/pmc_mux/conn
						use usb2_port1 as usb2_port
						use tcss_usb3_port1 as usb3_port
						device generic 0 alias conn0 on end
					end
					chip drivers/intel/pmc_mux/conn
						use usb2_port3 as usb2_port
						use tcss_usb3_port3 as usb3_port
						device generic 1 alias conn1 on end
					end
				end
			end
		end
		device ref tcss_xhci on
			chip drivers/usb/acpi
				device ref tcss_root_hub on
					chip drivers/usb/acpi
						register "desc" = ""USB3 Type-C Port C0 (MLB)""
						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
						register "use_custom_pld" = "true"
						register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, RIGHT, ACPI_PLD_GROUP(1, 1))"
						device ref tcss_usb3_port1 on end
					end
					chip drivers/usb/acpi
						register "desc" = ""USB3 Type-C Port C2 (MLB)""
						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
						register "use_custom_pld" = "true"
						register "custom_pld" = "ACPI_PLD_TYPE_C(FRONT, RIGHT, ACPI_PLD_GROUP(2, 1))"
						device ref tcss_usb3_port3 on end
					end
				end
			end
		end
		device ref xhci on
			chip drivers/usb/acpi
				device ref xhci_root_hub on
					chip drivers/usb/acpi
						register "desc" = ""USB2 Type-C Port C0 (MLB)""
						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
						register "use_custom_pld" = "true"
						register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, RIGHT, ACPI_PLD_GROUP(1, 1))"
						device ref usb2_port1 on end
					end
					chip drivers/usb/acpi
						register "desc" = ""USB2 Type-C Port C2 (MLB)""
						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
						register "use_custom_pld" = "true"
						register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(2, 1))"
						device ref usb2_port3 on end
					end
					chip drivers/usb/acpi
						register "desc" = ""USB2 Type-A Port A4 (MLB)""
						register "type" = "UPC_TYPE_A"
						register "use_custom_pld" = "true"
						register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, LEFT, ACPI_PLD_GROUP(4, 1))"
						device ref usb2_port4 on end
					end
					chip drivers/usb/acpi
						register "desc" = ""USB2 NFC""
						register "type" = "UPC_TYPE_INTERNAL"
						device ref usb2_port5 on end
					end
					chip drivers/usb/acpi
						register "desc" = ""USB2 Type-A Port A3 (MLB)""
						register "type" = "UPC_TYPE_A"
						register "use_custom_pld" = "true"
						register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, CENTER, ACPI_PLD_GROUP(5, 1))"
						device ref usb2_port6 on end
					end
					chip drivers/usb/acpi
						register "desc" = ""USB2 Type-A Port A2 (MLB)""
						register "type" = "UPC_TYPE_A"
						register "use_custom_pld" = "true"
						register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, LEFT, ACPI_PLD_GROUP(6, 1))"
						device ref usb2_port7 on end
					end
					chip drivers/usb/acpi
						register "desc" = ""USB2 Type-A Port A1 (MLB)""
						register "type" = "UPC_TYPE_A"
						register "use_custom_pld" = "true"
						register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, CENTER, ACPI_PLD_GROUP(7, 1))"
						device ref usb2_port8 on end
					end
					chip drivers/usb/acpi
						register "desc" = ""USB2 Bluetooth""
						register "type" = "UPC_TYPE_INTERNAL"
						register "reset_gpio" =	"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
						device ref usb2_port10 on end
					end
					chip drivers/usb/acpi
						register "desc" = ""USB3 Type-A Port A1 (MLB)""
						register "type" = "UPC_TYPE_USB3_A"
						register "use_custom_pld" = "true"
						register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, CENTER, ACPI_PLD_GROUP(7, 2))"
						device ref usb3_port1 on end
					end
					chip drivers/usb/acpi
						register "desc" = ""USB3 Type-A Port A2 (MLB)""
						register "type" = "UPC_TYPE_USB3_A"
						register "use_custom_pld" = "true"
						register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, LEFT, ACPI_PLD_GROUP(6, 1))"
						device ref usb3_port2 on end
					end
					chip drivers/usb/acpi
						register "desc" = ""USB3 Type-A Port A3 (MLB)""
						register "type" = "UPC_TYPE_USB3_A"
						register "use_custom_pld" = "true"
						register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, CENTER, ACPI_PLD_GROUP(5, 1))"
						device ref usb3_port3 on end
					end
					chip drivers/usb/acpi
						register "desc" = ""USB3 Type-A Port A4 (MLB)""
						register "type" = "UPC_TYPE_USB3_A"
						register "use_custom_pld" = "true"
						register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, LEFT, ACPI_PLD_GROUP(4, 1))"
						device ref usb3_port4 on end
					end
				end
			end
		end # USB2 and USB3 Port
	end

end