fw_config field STORAGE 2 3 option STORAGE_UNKNOWN 0 option STORAGE_UFS 1 option STORAGE_NVME 2 end field WIFI_BT 4 4 option WIFI_BT_CNVI 0 option WIFI_BT_PCIE 1 end field DB_USB 11 12 option DB_1A 0 option DB_1A_LTE 1 end field FPMCU 17 18 option FPMCU_ABSENT 0 option FPMCU_NUVOTON 1 end end chip soc/intel/alderlake register "platform_pmax" = "208" register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C0 register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable USB2 Port register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C2 register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # WWAN register "usb2_ports[4]" = "USB2_PORT_EMPTY" # Disable USB2 Port register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Camera register "usb2_ports[6]" = "USB2_PORT_MID(OC2)" # Type-A Port A0 register "usb2_ports[7]" = "USB2_PORT_EMPTY" # Disable USB2 Port register "usb2_ports[8]" = "USB2_PORT_MID(OC1)" # Type-A Port A1 register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Bluetooth register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # Type-A port A1(DB) register "usb3_ports[1]" = "USB3_PORT_EMPTY" # Disable USB3 Port register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" # Type A port A0(DCI) register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # WWAN device domain 0 on device ref dtt on chip drivers/intel/dptf ## sensor information register "options.tsr[0].desc" = ""DRAM_SOC"" register "options.tsr[1].desc" = ""Fan-Inlet"" ## Active Policy register "policies.active" = "{ [0] = { .target = DPTF_CPU, .thresholds = { TEMP_PCT(95, 90), TEMP_PCT(92, 80), TEMP_PCT(89, 60), TEMP_PCT(85, 40), TEMP_PCT(80, 30), } }, [1] = { .target = DPTF_TEMP_SENSOR_0, .thresholds = { TEMP_PCT(54, 95), TEMP_PCT(52, 90), TEMP_PCT(50, 80), TEMP_PCT(48, 50), TEMP_PCT(46, 30), TEMP_PCT(44, 25), TEMP_PCT(42, 20), TEMP_PCT(40, 15), } }, [2] = { .target = DPTF_TEMP_SENSOR_1, .thresholds = { TEMP_PCT(54, 95), TEMP_PCT(52, 90), TEMP_PCT(50, 80), TEMP_PCT(48, 50), TEMP_PCT(46, 30), TEMP_PCT(44, 25), TEMP_PCT(42, 20), TEMP_PCT(40, 15), } } }" ## Passive Policy register "policies.passive" = "{ [0] = DPTF_PASSIVE(CPU, CPU, 97, 5000), [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 85, 5000), [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 85, 5000), }" ## Critical Policy register "policies.critical" = "{ [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 95, SHUTDOWN), [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 95, SHUTDOWN), }" register "controls.power_limits" = "{ .pl1 = { .min_power = 15000, .max_power = 15000, .time_window_min = 28 * MSECS_PER_SEC, .time_window_max = 32 * MSECS_PER_SEC, .granularity = 200, }, .pl2 = { .min_power = 55000, .max_power = 55000, .time_window_min = 28 * MSECS_PER_SEC, .time_window_max = 32 * MSECS_PER_SEC, .granularity = 1000, } }" ## Charger Performance Control (Control, mA) register "controls.charger_perf" = "{ [0] = { 255, 1700 }, [1] = { 24, 1500 }, [2] = { 16, 1000 }, [3] = { 8, 500 } }" ## Fan Performance Control (Percent, Speed, Noise, Power) register "controls.fan_perf" = "{ [0] = { 90, 6700, 220, 2200, }, [1] = { 80, 5800, 180, 1800, }, [2] = { 70, 5000, 145, 1450, }, [3] = { 60, 4900, 115, 1150, }, [4] = { 50, 3838, 90, 900, }, [5] = { 40, 2904, 55, 550, }, [6] = { 30, 2337, 30, 300, }, [7] = { 20, 1608, 15, 150, }, [8] = { 10, 800, 10, 100, }, [9] = { 0, 0, 0, 50, } }" ## Fan options register "options.fan.fine_grained_control" = "1" register "options.fan.step_size" = "2" device generic 0 alias dptf_policy on end end end # DTT device ref igpu on chip drivers/gfx/generic register "device_count" = "6" # DDIA for eDP register "device[0].name" = ""LCD0"" register "device[0].type" = "panel" # DDIB for HDMI # If HDMI is not enumerated in the kernel, then no GFX device should be added for DDIB register "device[1].name" = ""DD01"" # TCP0 (DP-1) for port C0 register "device[2].name" = ""DD02"" register "device[2].use_pld" = "true" register "device[2].pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" # TCP1 (DP-2) is unused for any ports but still enumerated in the kernel, so GFX device is added for TCP1 register "device[3].name" = ""DD03"" # TCP2 (DP-3) for port C2 register "device[4].name" = ""DD04"" register "device[4].use_pld" = "true" register "device[4].pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))" # TCP3 (DP-4) is unused for any ports but still enumerated in the kernel, so GFX device is added for TCP3 register "device[5].name" = ""DD05"" device generic 0 on end end end # Integrated Graphics Device device ref pch_espi on chip ec/google/chromeec device pnp 0c09.0 on end end end device ref pmc hidden chip drivers/intel/pmc_mux device generic 0 on chip drivers/intel/pmc_mux/conn use usb2_port1 as usb2_port use tcss_usb3_port1 as usb3_port device generic 0 on end end chip drivers/intel/pmc_mux/conn use usb2_port3 as usb2_port use tcss_usb3_port3 as usb3_port device generic 1 on end end end end end device ref tcss_xhci on chip drivers/usb/acpi device ref tcss_root_hub on chip drivers/usb/acpi register "desc" = ""USB3 Type-C Port C0 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" device ref tcss_usb3_port1 on end end chip drivers/usb/acpi register "desc" = ""USB3 Type-C Port C2 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))" device ref tcss_usb3_port3 on end end end end end device ref xhci on chip drivers/usb/acpi device ref xhci_root_hub on chip drivers/usb/acpi register "desc" = ""USB2 Type-C Port C0 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" device ref usb2_port1 on end end chip drivers/usb/acpi register "desc" = ""USB2 Type-C Port C2 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))" device ref usb2_port3 on end end chip drivers/usb/acpi register "desc" = ""USB2 WWAN"" register "type" = "UPC_TYPE_INTERNAL" device ref usb2_port4 on probe DB_USB DB_1A_LTE end end chip drivers/usb/acpi register "desc" = ""USB2 Camera"" register "type" = "UPC_TYPE_INTERNAL" register "has_power_resource" = "1" register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E7)" device ref usb2_port6 on end end chip drivers/usb/acpi register "desc" = ""USB2 Type-A Port A0 (DCI)"" register "type" = "UPC_TYPE_A" register "use_custom_pld" = "true" register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(3, 1))" device ref usb2_port7 on end end chip drivers/usb/acpi register "desc" = ""USB2 Type-A Port A1 (DB)"" register "type" = "UPC_TYPE_A" register "use_custom_pld" = "true" register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, LEFT, ACPI_PLD_GROUP(4, 1))" device ref usb2_port9 on end end chip drivers/usb/acpi register "desc" = ""USB2 Bluetooth"" register "type" = "UPC_TYPE_INTERNAL" register "has_power_resource" = "1" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)" device ref usb2_port10 on end end chip drivers/usb/acpi register "desc" = ""USB3 Type-A Port A1 (DB)"" register "type" = "UPC_TYPE_USB3_A" register "use_custom_pld" = "true" register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, LEFT, ACPI_PLD_GROUP(4, 1))" device ref usb3_port1 on end end chip drivers/usb/acpi register "desc" = ""USB3 Type-A Port A0 (DCI)"" register "type" = "UPC_TYPE_USB3_A" register "use_custom_pld" = "true" register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(3, 1))" device ref usb3_port3 on end end chip drivers/usb/acpi register "desc" = ""USB3 WWAN"" register "type" = "UPC_TYPE_INTERNAL" device ref usb3_port4 on probe DB_USB DB_1A_LTE end end end end end device ref pcie4_0 on # Enable CPU PCIE RP 1 using CLK 3 register "cpu_pcie_rp[CPU_RP(1)]" = "{ .clk_req = 3, .clk_src = 3, .flags = PCIE_RP_LTR | PCIE_RP_AER, }" probe STORAGE STORAGE_NVME end device ref pcie_rp5 on register "pch_pcie_rp[PCH_RP(5)]" = "{ .clk_src = 1, .clk_req = 1, .flags = PCIE_RP_LTR | PCIE_RP_AER, }" chip drivers/wifi/generic register "wake" = "GPE0_DW0_03" register "add_acpi_dma_property" = "true" device pci 00.0 on probe WIFI_BT WIFI_BT_PCIE end end chip soc/intel/common/block/pcie/rtd3 # enable_gpio is controlled by the EC with EC_EN_PP3300_WLAN register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H2)" register "srcclk_pin" = "1" device generic 0 on end end probe WIFI_BT WIFI_BT_PCIE end device ref cnvi_wifi on chip drivers/wifi/generic register "wake" = "GPE0_PME_B0" register "add_acpi_dma_property" = "true" register "enable_cnvi_ddr_rfim" = "true" device generic 0 on end end probe WIFI_BT WIFI_BT_CNVI end device ref ish on chip drivers/intel/ish register "add_acpi_dma_property" = "true" device generic 0 alias ish_conf on end end probe STORAGE STORAGE_UFS end device ref ufs on probe STORAGE STORAGE_UFS end device ref i2c0 on chip drivers/i2c/generic register "hid" = ""ELAN0000"" register "desc" = ""ELAN Touchpad"" register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E3_IRQ)" register "wake" = "GPE0_DW2_03" register "detect" = "1" device i2c 0x15 on end end chip drivers/i2c/hid register "generic.hid" = ""SYNA0000"" register "generic.cid" = ""ACPI0C50"" register "generic.desc" = ""Synaptics Touchpad"" register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E3_IRQ)" register "generic.wake" = "GPE0_DW2_03" register "generic.detect" = "1" register "hid_desc_reg_offset" = "0x20" device i2c 0x2c on end end end #I2C0 device ref i2c1 on chip drivers/i2c/hid register "generic.hid" = ""ILTK0001"" register "generic.desc" = ""ILITEK Touchscreen"" register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F18_IRQ)" register "generic.detect" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F17)" register "generic.reset_delay_ms" = "200" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F7)" register "generic.enable_delay_ms" = "12" register "generic.has_power_resource" = "1" register "hid_desc_reg_offset" = "0x01" device i2c 41 on end end chip drivers/i2c/hid register "generic.hid" = ""ELAN9004"" register "generic.desc" = ""ELAN Touchscreen"" register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F18_IRQ)" register "generic.detect" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F17)" register "generic.reset_delay_ms" = "20" register "generic.reset_off_delay_ms" = "2" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F7)" register "generic.enable_delay_ms" = "1" register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F14)" register "generic.stop_delay_ms" = "150" register "generic.stop_off_delay_ms" = "2" register "generic.has_power_resource" = "1" register "hid_desc_reg_offset" = "0x01" device i2c 10 on end end end device ref i2c2 on chip drivers/i2c/generic register "hid" = ""RTL5682"" register "name" = ""RT58"" register "desc" = ""Headset Codec"" register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_S6)" # Set the jd_src to RT5668_JD1 for jack detection register "property_count" = "1" register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" register "property_list[0].name" = ""realtek,jd-src"" register "property_list[0].integer" = "1" device i2c 1a on end end chip drivers/generic/alc1015 register "hid" = ""RTL1019"" register "sdb" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F20)" device generic 0 on end end end device ref gspi1 on chip drivers/spi/acpi register "name" = ""CRFP"" register "hid" = "ACPI_DT_NAMESPACE_HID" register "uid" = "1" register "compat_string" = ""google,cros-ec-spi"" register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F15_IRQ)" register "wake" = "GPE0_DW2_15" register "has_power_resource" = "1" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D2)" register "enable_delay_ms" = "3" device spi 0 on probe FPMCU FPMCU_NUVOTON end end # FPMCU end device ref hda on chip drivers/sof register "spkr_tplg" = "rt1019" register "jack_tplg" = "rt5682" register "mic_tplg" = "_2ch_pdm0" device generic 0 on end end end end end