/* * This file is part of the coreboot project. * * Copyright (C) 2007-2009 coresystems GmbH * Copyright (C) 2012 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ #include <smbios.h> #include <string.h> #include <types.h> #include <arch/acpi.h> #include <arch/io.h> #include <arch/interrupt.h> #include <boot/coreboot_tables.h> #include <console/console.h> #include <device/device.h> #include <device/device.h> #include <device/pci_def.h> #include <device/pci_ops.h> #include <pc80/mc146818rtc.h> #include <southbridge/intel/lynxpoint/pch.h> #include <vendorcode/google/chromeos/chromeos.h> #include "onboard.h" void mainboard_suspend_resume(void) { /* Call SMM finalize() handlers before resume */ outb(0xcb, 0xb2); } static void mainboard_init(device_t dev) { lan_init(); } // mainboard_enable is executed as first thing after // enumerate_buses(). static void mainboard_enable(device_t dev) { dev->ops->init = mainboard_init; dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; } struct chip_operations mainboard_ops = { .enable_dev = mainboard_enable, };