uses HAVE_MP_TABLE uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT uses HAVE_HARD_RESET uses HAVE_OPTION_TABLE uses USE_OPTION_TABLE uses CONFIG_COMPRESS uses CONFIG_COMPRESSED_PAYLOAD_NRV2B uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD uses CONFIG_ROM_PAYLOAD uses IRQ_SLOT_COUNT uses MAINBOARD uses MAINBOARD_VENDOR uses MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION uses ARCH uses FALLBACK_SIZE uses STACK_SIZE uses HEAP_SIZE uses ROM_SIZE uses ROM_SECTION_SIZE uses ROM_IMAGE_SIZE uses ROM_SECTION_SIZE uses ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START uses PAYLOAD_SIZE uses _ROMBASE uses _RAMBASE uses XIP_ROM_SIZE uses XIP_ROM_BASE uses HAVE_MP_TABLE uses CROSS_COMPILE uses CC uses HOSTCC uses OBJCOPY uses CONFIG_CONSOLE_SERIAL8250 uses DEFAULT_CONSOLE_LOGLEVEL uses MAXIMUM_CONSOLE_LOGLEVEL default CONFIG_CONSOLE_SERIAL8250=1 default DEFAULT_CONSOLE_LOGLEVEL=8 default MAXIMUM_CONSOLE_LOGLEVEL=8 ## ROM_SIZE is the size of boot ROM that this board will use. default ROM_SIZE = 256*1024 ### ### Build options ### ## ## Build code for the fallback boot ## default HAVE_FALLBACK_BOOT=1 ## ## no MP table ## default HAVE_MP_TABLE=0 ## ## Build code to reset the motherboard from coreboot ## default HAVE_HARD_RESET=0 ## ## Build code to export a programmable irq routing table ## default HAVE_PIRQ_TABLE=1 default IRQ_SLOT_COUNT=6 ## ## Build code to export a CMOS option table ## default HAVE_OPTION_TABLE=1 ### ### coreboot layout values ### ## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default ROM_IMAGE_SIZE = 65536 default FALLBACK_SIZE = 131072 ## ## Use a small 8K stack ## default STACK_SIZE=0x2000 ## ## Use a small 16K heap ## default HEAP_SIZE=0x4000 ## ## Only use the option table in a normal image ## #default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE default USE_OPTION_TABLE = 0 default _RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## default CC="$(CROSS_COMPILE)gcc -m32" default HOSTCC="gcc" end