/* * This file is part of the coreboot project. * * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ /* DefinitionBlock Statement */ DefinitionBlock ( "DSDT.AML", /* Output filename */ "DSDT", /* Signature */ 0x02, /* DSDT Revision, needs to be 2 for 64bit */ "AMD ", /* OEMID */ "COREBOOT", /* TABLE ID */ 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */ #include "acpi/mainboard.asl" #include <cpu/amd/agesa/family14/acpi/cpu.asl> #include "acpi/routing.asl" Scope(\_SB) { /* global utility methods expected within the \_SB scope */ #include <arch/x86/acpi/globutil.asl> Device(PCI0) { /* Describe the AMD Northbridge */ #include <northbridge/amd/agesa/family14/acpi/northbridge.asl> /* Describe the AMD Fusion Controller Hub Southbridge */ #include <southbridge/amd/cimx/sb800/acpi/fch.asl> /* Primary (and only) IDE channel */ Device(IDEC) { Name(_ADR, 0x00140001) #include "acpi/ide.asl" } /* end IDEC */ } } /* End Scope(_SB) */ /* Contains the supported sleep states for this chipset */ #include <southbridge/amd/cimx/sb800/acpi/sleepstates.asl> /* Contains the Sleep methods (WAK, PTS, GTS, etc.) */ #include "acpi/sleep.asl" #include "acpi/gpe.asl" } /* End of ASL file */