##
## Compute the location and size of where this firmware image
## (coreboot plus bootloader) will live in the boot rom chip.
##
if USE_FALLBACK_IMAGE
	default ROM_SECTION_SIZE   = FALLBACK_SIZE
	default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
else
	default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE )
	default ROM_SECTION_OFFSET = 0
end

##
## Compute the start location and size size of
## The coreboot bootloader.
##
default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)

##
## Compute where this copy of coreboot will start in the boot rom
##
default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )

##
## Compute a range of ROM that can cached to speed up coreboot,
## execution speed.
##
## XIP_ROM_SIZE must be a power of 2.
## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
##
default XIP_ROM_SIZE=65536
default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )

##
## Set all of the defaults for an x86 architecture
##

arch i386 end

##
## Build the objects we have code for in this directory.
##

driver mainboard.o
if HAVE_PIRQ_TABLE object irq_tables.o end
#object reset.o

##
## Romcc output
##
makerule ./failover.E
	depends "$(MAINBOARD)/failover.c ./romcc" 
	action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end

makerule ./failover.inc
	depends "$(MAINBOARD)/failover.c ./romcc"
	action "./romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end

makerule ./auto.E 
	depends	"$(MAINBOARD)/auto.c option_table.h ./romcc" 
	action	"./romcc -E -mcpu=p3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end
makerule ./auto.inc 
	depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
	action	"./romcc    -mcpu=p3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end

##
## Build our 16 bit and 32 bit coreboot entry code
##
mainboardinit cpu/x86/16bit/entry16.inc
mainboardinit cpu/x86/32bit/entry32.inc
ldscript /cpu/x86/16bit/entry16.lds
ldscript /cpu/x86/32bit/entry32.lds

##
## Build our reset vector (This is where coreboot is entered)
##
if USE_FALLBACK_IMAGE 
	mainboardinit cpu/x86/16bit/reset16.inc 
	ldscript /cpu/x86/16bit/reset16.lds 
else
	mainboardinit cpu/x86/32bit/reset32.inc 
	ldscript /cpu/x86/32bit/reset32.lds 
end

### Should this be in the northbridge code?
mainboardinit arch/i386/lib/cpu_reset.inc

##
## Include an id string (For safe flashing)
##
mainboardinit arch/i386/lib/id.inc
ldscript /arch/i386/lib/id.lds

###
### This is the early phase of coreboot startup 
### Things are delicate and we test to see if we should
### failover to another image.
###
if USE_FALLBACK_IMAGE
	ldscript /arch/i386/lib/failover.lds 
	mainboardinit ./failover.inc
end

###
### O.k. We aren't just an intermediary anymore!
###

##
## Setup RAM
##
mainboardinit cpu/x86/fpu/enable_fpu.inc
mainboardinit cpu/x86/mmx/enable_mmx.inc
mainboardinit cpu/x86/sse/enable_sse.inc
mainboardinit ./auto.inc
mainboardinit cpu/x86/sse/disable_sse.inc
mainboardinit cpu/x86/mmx/disable_mmx.inc

##
## Include the secondary Configuration files 
##
dir /pc80
config chip.h

## This does not look right but it is a literal conversion of the
## old version of this file.
chip northbridge/intel/i855pm
	device pci_domain 0 on 
		device pci 0.0 on end
		device pci 1.0 on end
		chip southbridge/intel/i82801dbm
#			pci 11.0 on end
#			pci 11.1 on end
#			pci 11.2 on end
#			pci 11.3 on end
#			pci 11.4 on end
#			pci 11.5 on end
#			pci 11.6 on end
#			pci 12.0 on end
			register "enable_usb" = "0"
			register "enable_native_ide" = "0"
			register "enable_usb" = "0"
			register "enable_native_ide" = "0"
			chip superio/winbond/w83627hf # link 1
                	        device pnp 2e.0 on      #  Floppy
                	                 io 0x60 = 0x3f0
                	                irq 0x70 = 6
                	                drq 0x74 = 2
				end
                	        device pnp 2e.1 off     #  Parallel Port
                	                 io 0x60 = 0x378
                	                irq 0x70 = 7
				end
                	        device pnp 2e.2 on      #  Com1
                	                 io 0x60 = 0x3f8
                	                irq 0x70 = 4
				end
                	        device pnp 2e.3 off     #  Com2
                	                io 0x60 = 0x2f8
                	                irq 0x70 = 3
				end
                	        device pnp 2e.5 on      #  Keyboard
                	                 io 0x60 = 0x60
                	                 io 0x62 = 0x64
                	                irq 0x70 = 1
					irq 0x72 = 12
				end
                	        device pnp 2e.6 off end #  CIR
                	        device pnp 2e.7 off end #  GAME_MIDI_GIPO1
                	        device pnp 2e.8 off end #  GPIO2
                	        device pnp 2e.9 off end #  GPIO3
                	        device pnp 2e.a off end #  ACPI
                	        device pnp 2e.b on      #  HW Monitor
 					 io 0x60 = 0x290
				end
				register "com1" = "{1}"
			#	register "com1" = "{1, 0, 0x3f8, 4}"
			#	register "lpt" = "{1}"
                	end
		end
	end
	device apic_cluster 0 on 
		chip cpu/intel/socket_mPGA479M
			device apic 0 on end
		end
	end
end