# SPDX-License-Identifier: GPL-2.0-only

chip soc/intel/skylake
	register "gpu_pp_up_delay_ms"		  = "200"	# T3
	register "gpu_pp_down_delay_ms"		  = "  0"	# T10
	register "gpu_pp_cycle_delay_ms"	  = "500"	# T12
	register "gpu_pp_backlight_on_delay_ms"	  = " 50"	# T7
	register "gpu_pp_backlight_off_delay_ms"  = "  0"	# T9

	register "gpu_pch_backlight_pwm_hz"	  = "200"

	# IGD Displays
	register "gfx" = "GMA_STATIC_DISPLAYS(0)"

	# FSP Configuration
	register "SkipExtGfxScan" = "1"
	register "SaGv" = "SaGv_Enabled"
	register "eist_enable" = "1"

	register "PmConfigSlpS3MinAssert" = "2"		# 50ms
	register "PmConfigSlpS4MinAssert" = "1"		# 1s
	register "PmConfigSlpSusMinAssert" = "3"	# 500ms
	register "PmConfigSlpAMinAssert" = "3"		# 2s

	# Send an extra VR mailbox command for the PS4 exit issue
	register "SendVrMbxCmd" = "2"

	register "power_limits_config" = "{
		.tdp_pl1_override = 20,
		.tdp_pl2_override = 30,
	}"

	register "common_soc_config" = "{
		.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
	}"

	register "SerialIoDevMode" = "{
		[PchSerialIoIndexUart2] = PchSerialIoSkipInit, // LPSS UART
	}"

	device cpu_cluster 0 on
		device lapic 0 on end
	end
	device domain 0 on
		subsystemid 0x1558 0x1313 inherit
		device pci 00.0 on	end # Host Bridge
		device pci 02.0 on	end # Integrated Graphics Device
		device pci 04.0 on	end # SA thermal subsystem
		device pci 05.0 off	end # Imaging Unit
		device pci 08.0 on	end # Gaussian Mixture Model
		device pci 13.0 off	end # Sensor Hub
		device pci 14.0 on	    # USB xHCI
			register "SsicPortEnable" = "0"
			# USB2
			register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)"	# Type-A, right
			register "usb2_ports[1]" = "USB2_PORT_FLEX(OC_SKIP)"	# 3G / LTE
			register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)"	# Type-C, right
			register "usb2_ports[3]" = "USB2_PORT_FLEX(OC_SKIP)"	# Camera
			register "usb2_ports[4]" = "USB2_PORT_FLEX(OC_SKIP)"	# Bluetooth
			register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)"	# Type-A, left
			register "usb2_ports[7]" = "USB2_PORT_TYPE_C(OC_SKIP)"	# Type-C, right
			# USB3
			register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A, right
			register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# 4G
			register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# Type C, right
			register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# Type-A, left
		end
		device pci 14.1 off	end # USB xDCI (OTG)
		device pci 14.2 on	end # Thermal Subsystem
		device pci 14.3 off	end # Camera
		device pci 15.0 off	end # I2C0
		device pci 15.1 off	end # I2C1
		device pci 15.2 off	end # I2C2
		device pci 15.3 off	end # I2C3
		device pci 16.0 on	    # Management Engine Interface 1
			register "HeciEnabled" = "1"
		end
		device pci 16.1 off	end # Management Engine Interface 2
		device pci 16.2 off	end # Management Engine IDE-R
		device pci 16.3 off	end # Management Engine KT Redirection
		device pci 16.4 off	end # Management Engine Interface 3
		device pci 17.0	on	    # SATA
			register "SataMode" = "SATA_AHCI"
			register "SataSalpSupport" = "0"
			# Ports
			register "SataPortsEnable[0]" = "1"
			register "SataPortsEnable[2]" = "1"
			register "SataPortsDevSlp[2]" = "1"
		end
		device pci 19.0 on	end # UART 2
		device pci 19.1 off	end # I2C5
		device pci 19.2 off	end # I2C4
		device pci 1c.0 on	    # PCI Express Port 1
			device pci 00.0 on end # x4 TBT
			register "PcieRpEnable[0]" = "1"
			register "PcieRpClkReqSupport[0]" = "1"
			register "PcieRpClkReqNumber[0]" = "4"
			register "PcieRpClkSrcNumber[0]" = "4"
			register "PcieRpHotPlug[0]" = "1"
			register "PcieRpLtrEnable[0]" = "1"
			smbios_slot_desc "SlotTypePciExpressGen3X4" "SlotLengthOther" "Thunderbolt/Type-C" "SlotDataBusWidth4X"
		end
		device pci 1c.1 off	end # PCI Express Port 2
		device pci 1c.2 off	end # PCI Express Port 3
		device pci 1c.3 off	end # PCI Express Port 4
		device pci 1c.4 on	    # PCI Express Port 5
			device pci 00.0 on end # x1 LAN
			register "PcieRpEnable[4]" = "1"
			register "PcieRpClkReqSupport[4]" = "1"
			register "PcieRpClkReqNumber[4]" = "3"
			register "PcieRpClkSrcNumber[4]" = "3"
			register "PcieRpLtrEnable[4]" = "1"
		end
		device pci 1c.5 on	    # PCI Express Port 6
			device pci 00.0 on end # x1 WLAN
			register "PcieRpEnable[5]" = "1"
			register "PcieRpClkReqSupport[5]" = "1"
			register "PcieRpClkReqNumber[5]" = "2"
			register "PcieRpClkSrcNumber[5]" = "2"
			register "PcieRpLtrEnable[5]" = "1"
			smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/A/E 2230 (J_WLAN1)" "SlotDataBusWidth1X"
		end
		device pci 1c.6 off	end # PCI Express Port 7
		device pci 1c.7 off	end # PCI Express Port 8
		device pci 1d.0 on	    # PCI Express Port 9
			device pci 00.0 on end # x4 M.2/M (J_SSD1)
			register "PcieRpEnable[8]" = "1"
			register "PcieRpClkReqSupport[8]" = "1"
			register "PcieRpClkReqNumber[8]" = "5"
			register "PcieRpClkSrcNumber[8]" = "5"
			register "PcieRpLtrEnable[8]" = "1"
			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD1)" "SlotDataBusWidth4X"
		end
		device pci 1d.1 off	end # PCI Express Port 10
		device pci 1d.2 off	end # PCI Express Port 11
		device pci 1d.3 off	end # PCI Express Port 12
		device pci 1e.0 off	end # UART 0
		device pci 1e.1	off	end # UART 1
		device pci 1e.2 off	end # GSPI 0
		device pci 1e.3 off	end # GSPI 1
		device pci 1e.4 off	end # eMMC
		device pci 1e.5 off	end # SDIO
		device pci 1e.6 off	end # SDXC
		device pci 1f.0 on	    # LPC Interface
			register "gen1_dec" = "0x000c0681"
			register "gen2_dec" = "0x000c1641"
			register "gen3_dec" = "0x000c0081"
			register "gen4_dec" = "0x00040069"
			register "serirq_mode" = "SERIRQ_CONTINUOUS"
			chip drivers/pc80/tpm
				device pnp 0c31.0 on end
			end
		end
		device pci 1f.1 hidden	end # P2SB
		device pci 1f.2 on	    # Power Management Controller
			register "gpe0_dw0" = "GPP_C"
			register "gpe0_dw1" = "GPP_D"
			register "gpe0_dw2" = "GPP_E"
		end
		device pci 1f.3 on	end # Intel HDA
		device pci 1f.4 on	end # SMBus
		device pci 1f.5 on	end # PCH SPI
		device pci 1f.6 off	end # GbE
		device pci 1f.7 off	end # Trace Hub
	end
end