## SPDX-License-Identifier: GPL-2.0-only

chip northbridge/intel/sandybridge
	# All MRC-capable boards in family (P8Z77-M[ PRO]) lists supported
	# DIMMs down to 1.25v
	register "ddr3lv_support" = "1"
	# FIXME: Nothing can run native at 800MHz on p8z77-m, others may have same problem
	register "max_mem_clock_mhz" = "CONFIG(USE_NATIVE_RAMINIT) ? 666 : 800"

	register "usb_port_config" = "{
		{1, 0, 0x0080}, {1, 0, 0x0080}, {1, 1, 0x0080}, {1, 1, 0x0080}, {1, 2, 0x0080},
		{1, 2, 0x0080}, {1, 3, 0x0080}, {1, 3, 0x0080}, {1, 4, 0x0080}, {1, 4, 0x0080},
		{1, 6, 0x0080}, {1, 5, 0x0080}, {1, 5, 0x0080}, {1, 6, 0x0080}
		}"
	# 4 bit switch mask. 0=not switchable, 1=switchable
	# Means once it's loaded the OS, it can swap ports
	# from/to EHCI/xHCI. Z77 has four USB3 ports, so 0xf
	register "usb3.hs_port_switch_mask" = "0xf"
	# (The other 3 usb3.* settings can be set from nvram options, and so are set
	# from runtime code)

	device domain 0 on
		device ref host_bridge on  end		# Host bridge
		device ref peg10 on  end		# PCIEX16_1
		device ref igd on  end		# iGPU

		chip southbridge/intel/bd82x6x
			register "sata_interface_speed_support" = "0x3"
			register "sata_port_map" = "0x3f"
			register "spi_lvscc" = "0x2005"
			register "spi_uvscc" = "0x2005"
			register "superspeed_capable_ports" = "0x0000000f"
			register "xhci_overcurrent_mapping" = "0x00000c03"
			register "xhci_switchable_ports"    = "0x0000000f"

			device ref xhci on  end		# xHCI
			device ref mei1 on  end		# MEI #1
			device ref mei2 off end		# MEI #2
			device ref me_ide_r off end		# ME IDE-R
			device ref me_kt off end		# ME KT
			device ref gbe off end		# Intel GbE
			device ref ehci2 on  end		# EHCI #2
			device ref hda on  end		# HD Audio

			device ref pcie_rp1 off end		# RP #1
			device ref pcie_rp2 off end		# RP #2
			device ref pcie_rp3 off end		# RP #3
			device ref pcie_rp4 off end		# RP #4
			device ref pcie_rp5 off end		# RP #5
			device ref pcie_rp6 off end		# RP #6
			device ref pcie_rp7 off end		# RP #7
			device ref pcie_rp8 off end		# RP #8

			device ref ehci1 on  end		# EHCI #1
			device ref pci_bridge off end		# PCI bridge
			device ref lpc on		# LPC bridge
			end
			device ref sata1 on  end		# SATA (AHCI)
			device ref smbus on  end		# SMBus
			device ref sata2 off end		# SATA (Legacy)
			device ref thermal off end		# Thermal
		end
	end
end