## SPDX-License-Identifier: GPL-2.0-only

chip northbridge/intel/sandybridge
	# All MRC-capable boards in family (P8Z77-M[ PRO]) lists supported
	# DIMMs down to 1.25v
	register "ddr3lv_support" = "1"
	register "max_mem_clock_mhz" = "800"
	register "spd_addresses" = "{0x50, 0x51, 0x52, 0x53}"

	# 4 bit switch mask. 0=not switchable, 1=switchable
	# Means once it's loaded the OS, it can swap ports
	# from/to EHCI/xHCI. Z77 has four USB3 ports, so 0xf
	register "usb3.hs_port_switch_mask" = "0xf"
	# (The other 3 usb3.* settings can be set from nvram options, and so are set
	# from runtime code)

	device domain 0 on
		device ref host_bridge on  end
		device ref peg10 on  end # PCIEX16_1
		device ref igd on  end

		chip southbridge/intel/bd82x6x
			register "sata_interface_speed_support" = "0x3"
			register "sata_port_map" = "0x3f"
			register "spi_lvscc" = "0x2005"
			register "spi_uvscc" = "0x2005"
			register "superspeed_capable_ports" = "0x0000000f"
			register "xhci_overcurrent_mapping" = "0x00000c03"
			register "xhci_switchable_ports"    = "0x0000000f"

			device ref xhci on  end
			device ref mei1 on  end
			device ref mei2 off end
			device ref me_ide_r off end
			device ref me_kt off end
			device ref gbe off end
			device ref ehci2 on  end
			device ref hda on  end

			device ref pcie_rp1 off end
			device ref pcie_rp2 off end
			device ref pcie_rp3 off end
			device ref pcie_rp4 off end
			device ref pcie_rp5 off end
			device ref pcie_rp6 off end
			device ref pcie_rp7 off end
			device ref pcie_rp8 off end

			device ref ehci1 on  end
			device ref pci_bridge off end
			device ref lpc on end
			device ref sata1 on  end # SATA (AHCI)
			device ref smbus on  end
			device ref sata2 off end # SATA (Legacy)
			device ref thermal off end
		end
	end
end