#
# This file is part of the coreboot project.
#
# Copyright (C) 2017 Arthur Heymans <arthur@aheymans.xyz>
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
# GNU General Public License for more details.
#

chip northbridge/intel/x4x		# Northbridge
	device cpu_cluster 0 on		# APIC cluster
		chip cpu/intel/socket_LGA775
			device lapic 0 on end
		end
		chip cpu/intel/model_1067x		# CPU
			device lapic 0xACAC off end
		end
	end
	device domain 0 on		# PCI domain
		subsystemid 0x1043 0x836d inherit
		device pci 0.0 on end			# Host Bridge
		device pci 1.0 on end			# PEG
		device pci 2.0 on end			# Integrated graphics controller
		chip southbridge/intel/i82801gx	# Southbridge
			register "pirqa_routing" = "0x0b"
			register "pirqb_routing" = "0x0b"
			register "pirqc_routing" = "0x0b"
			register "pirqd_routing" = "0x0b"
			register "pirqe_routing" = "0x80"
			register "pirqf_routing" = "0x80"
			register "pirqg_routing" = "0x80"
			register "pirqh_routing" = "0x0b"
			# GPI routing
			#  0 No effect (default)
			#  1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
			#  2 SCI (if corresponding GPIO_EN bit is also set)

			register "ide_enable_primary" = "0x1"
			register "sata_ahci" = "0x0" # AHCI not supported on this ICH7 variant
			register "gpe0_en" = "0x04000440"

			device pci 1b.0 on end		# Audio
			device pci 1c.0 on end		# PCIe 1
			device pci 1c.1 on		# PCIe 2: NIC
				device pci 00.0 on
				end
			end
			device pci 1c.2 off end		# PCIe 3
			device pci 1c.3 off end		# PCIe 4
			device pci 1c.4 off end		# PCIe 5
			device pci 1c.5 off end		# PCIe 6
			device pci 1d.0 on end		# USB
			device pci 1d.1 on end		# USB
			device pci 1d.2 on end		# USB
			device pci 1d.3 on end		# USB
			device pci 1d.7 on end		# USB
			device pci 1e.0 on end		# PCI bridge
			device pci 1e.2 off end		# AC'97 Audio Controller
			device pci 1e.3 off end		# AC'97 Modem Controller
			device pci 1f.0 on		# ISA bridge
				chip superio/winbond/w83627dhg
					device pnp 2e.0 off end		# Floppy
					device pnp 2e.1 on		# Parallel port
						# global
						irq 0x2c = 0x92
						# parallel port
						io 0x60 = 0x378
						irq 0x70 = 7
						drq 0x74 = 3
					end
					device pnp 2e.2 on		# COM1
						io 0x60 = 0x3f8
						irq 0x70 = 4
					end
					device pnp 2e.3 off end		# COM2, IR
					device pnp 2e.5 on		# Keyboard, mouse
						io 0x60 = 0x60
						io 0x62 = 0x64
						irq 0x70 = 1
						irq 0x72 = 12
					end
					device pnp 2e.6 off end		# SPI
					device pnp 2e.7 on end		# GPIO6 (all input)
					device pnp 2e.8 off end		# WDT0#, PLED
					device pnp 2e.9 off end		# GPIO2
					device pnp 2e.109 on		# GPIO3
						irq 0xf0 = 0xf3
#						irq 0xf1 = 0x08
					end
					device pnp 2e.209 on		# GPIO4
						irq 0xf4 = 0x00
					end
					device pnp 2e.309 off end		# GPIO5
					device pnp 2e.a on		# ACPI
						irq 0x70 = 0
						irq 0xe4 = 0x10 # VSBGATE# to power dram during S3
					end
					device pnp 2e.b on		# HWM, front pannel LED
						io 0x60 = 0x290
						irq 0x70 = 0
					end
					device pnp 2e.c on		# PECI, SST
						irq 0xe0 = 0x10
						irq 0xe1 = 0x64
                                                irq 0xe8 = 0x01
					end
				end
			end
			device pci 1f.1 on end	# PATA/IDE
			device pci 1f.2 on end	# SATA
			device pci 1f.3 on end	# SMbus
		end
	end
end