chip northbridge/amd/amdfam10/root_complex	# Root complex
	device cpu_cluster 0 on			# (L)APIC cluster
		chip cpu/amd/socket_F_1207			# CPU socket
			device lapic 0 on end			# Local APIC of the CPU
		end
	end
	device domain 0 on			# PCI domain
		subsystemid 0x1043 0x8163 inherit
		chip northbridge/amd/amdfam10		# Northbridge / RAM controller
			register "maximum_memory_capacity" = "0x4000000000"	# 256GB
			device pci 18.0 on end		# Link 0 == LDT 0
			device pci 18.0 on end		# Link 1 == LDT 1
			device pci 18.0 on end		# Link 2 == LDT 2
			device pci 18.0 on		# Link 3 == LDT 3 [SB on link 3]
				chip southbridge/amd/sr5650		# Primary southbridge
					device pci 0.0 on end			# HT Root Complex 0x9600
					device pci 0.1 on end			# CLKCONFIG
					device pci 0.2 on end			# IOMMU
					device pci 2.0 on			# PCIE P2P bridge 0x9603 (GPP1 Port0)
						# Slot				# PCI E 1 / PCI E 2
					end
					device pci 3.0 off end			# PCIE P2P bridge 0x960b (GPP1 Port1)
					device pci 4.0 on			# PCIE P2P bridge 0x9604 (GPP3a Port0)
						# PIKE SAS
					end
					device pci 5.0 off end			# PCIE P2P bridge 0x9605 (GPP3a Port1)
					device pci 6.0 off end			# PCIE P2P bridge 0x9606 (GPP3a Port2)
					device pci 7.0 off end			# PCIE P2P bridge 0x9607 (GPP3a Port3)
					device pci 8.0 off end			# NB/SB Link P2P bridge
					device pci 9.0 on			# Bridge (GPP3a Port4)
						# Onboard			# NIC A
					end
					device pci a.0 on			# Bridge (GPP3a Port5)
						# Onboard			# NIC B
					end
					device pci b.0 on			# Bridge (GPP2 Port0)
						# Slot				# PCI E 4
					end
					device pci c.0 on			# Bridge (GPP2 Port1)
						# Slot				# PCI E 5
					end
					device pci d.0 on			# Bridge (GPP3b Port0)
						# Slot				# PCI E 3
					end
					register "gpp1_configuration" = "0"	# Configuration 16:0 default
					register "gpp2_configuration" = "1"	# Configuration 8:8
					register "gpp3a_configuration" = "2"	# Configuration 4:1:1:0:0:0
					register "port_enable" = "0x3f1c"	# Enable all ports except 0, 1, 5, 6, and 7
					register "pcie_settling_time" = "1000000"	# Allow PIKE to be detected / configured
				end
				chip southbridge/amd/sb700		# Secondary southbridge
					device pci 11.0 on end			# SATA
					device pci 12.0 on end			# USB
					device pci 12.1 on end			# USB
					device pci 12.2 on end			# USB
					device pci 13.0 on end			# USB
					device pci 13.1 on end			# USB
					device pci 13.2 on end			# USB
					device pci 14.0 on			# SM
						chip drivers/generic/generic	# DIMM n-0-0-0
							device i2c 50 on end
						end
						chip drivers/generic/generic	# DIMM n-0-0-1
							device i2c 51 on end
						end
						chip drivers/generic/generic	# DIMM n-0-1-0
							device i2c 52 on end
						end
						chip drivers/generic/generic	# DIMM n-0-1-1
							device i2c 53 on end
						end
						chip drivers/generic/generic	# DIMM n-1-0-0
							device i2c 54 on end
						end
						chip drivers/generic/generic	# DIMM n-1-0-1
							device i2c 55 on end
						end
						chip drivers/generic/generic	# DIMM n-1-1-0
							device i2c 56 on end
						end
						chip drivers/generic/generic	# DIMM n-1-1-1
							device i2c 57 on end
						end
						chip drivers/i2c/w83795
							register "fanin_ctl1" = "0xff"			# Enable monitoring of FANIN1 - FANIN8
							register "fanin_ctl2" = "0x00"			# Connect FANIN11 - FANIN14 to alternate functions
							register "temp_ctl1" = "0x2a"			# Enable monitoring of DTS, VSEN12, and VSEN13
							register "temp_ctl2" = "0x01"			# Enable monitoring of TD1/TR1
							register "temp_dtse" = "0x03"			# Enable DTS1 and DTS2
							register "volt_ctl1" = "0xff"			# Enable monitoring of VSEN1 - VSEN8
							register "volt_ctl2" = "0xf7"			# Enable monitoring of VSEN9 - VSEN11, 3VDD, 3VSB, and VBAT
							register "temp1_fan_select" = "0x00"		# All fans to manual mode (no dependence on Temp1)
							register "temp2_fan_select" = "0x00"		# All fans to manual mode (no dependence on Temp2)
							register "temp3_fan_select" = "0x00"		# All fans to manual mode (no dependence on Temp3)
							register "temp4_fan_select" = "0x00"		# All fans to manual mode (no dependence on Temp4)
							register "temp5_fan_select" = "0x00"		# All fans to manual mode (no dependence on Temp5)
							register "temp6_fan_select" = "0x00"		# All fans to manual mode (no dependence on Temp6)
							register "temp1_source_select" = "0x00"		# Use TD1/TR1 as data source for Temp1
							register "temp2_source_select" = "0x00"		# Use TD2/TR2 as data source for Temp2
							register "temp3_source_select" = "0x00"		# Use TD3/TR3 as data source for Temp3
							register "temp4_source_select" = "0x00"		# Use TD4/TR4 as data source for Temp4
							register "temp5_source_select" = "0x00"		# Use TR5 as data source for Temp5
							register "temp6_source_select" = "0x00"		# Use TR6 as data source for Temp6
							register "tr1_critical_temperature" = "85"	# Set TD1/TR1 critical temperature to 85°C
							register "tr1_critical_hysteresis" = "80"	# Set TD1/TR1 critical hysteresis temperature to 80°C
							register "tr1_warning_temperature" = "70"	# Set TD1/TR1 warning temperature to 70°C
							register "tr1_warning_hysteresis" = "65"	# Set TD1/TR1 warning hysteresis temperature to 65°C
							register "dts_critical_temperature" = "85"	# Set DTS (CPU) critical temperature to 85°C
							register "dts_critical_hysteresis" = "80"	# Set DTS (CPU) critical hysteresis temperature to 80°C
							register "dts_warning_temperature" = "70"	# Set DTS (CPU) warning temperature to 70°C
							register "dts_warning_hysteresis" = "65"	# Set DTS (CPU) warning hysteresis temperature to 65°C
							register "temp1_critical_temperature" = "80"	# Set Temp1 critical temperature to 80°C
							register "temp2_critical_temperature" = "80"	# Set Temp1 critical temperature to 80°C
							register "temp3_critical_temperature" = "80"	# Set Temp1 critical temperature to 80°C
							register "temp4_critical_temperature" = "80"	# Set Temp1 critical temperature to 80°C
							register "temp5_critical_temperature" = "80"	# Set Temp1 critical temperature to 80°C
							register "temp6_critical_temperature" = "80"	# Set Temp1 critical temperature to 80°C
							register "temp1_target_temperature" = "80"	# Set Temp1 target temperature to 80°C
							register "temp2_target_temperature" = "80"	# Set Temp1 target temperature to 80°C
							register "temp3_target_temperature" = "80"	# Set Temp1 target temperature to 80°C
							register "temp4_target_temperature" = "80"	# Set Temp1 target temperature to 80°C
							register "temp5_target_temperature" = "80"	# Set Temp1 target temperature to 80°C
							register "temp6_target_temperature" = "80"	# Set Temp1 target temperature to 80°C
							register "fan1_nonstop" = "7"			# Set Fan 1 minimum speed
							register "fan2_nonstop" = "7"			# Set Fan 2 minimum speed
							register "fan3_nonstop" = "7"			# Set Fan 3 minimum speed
							register "fan4_nonstop" = "7"			# Set Fan 4 minimum speed
							register "fan5_nonstop" = "7"			# Set Fan 5 minimum speed
							register "fan6_nonstop" = "7"			# Set Fan 6 minimum speed
							register "fan7_nonstop" = "7"			# Set Fan 7 minimum speed
							register "fan8_nonstop" = "7"			# Set Fan 8 minimum speed
							register "default_speed" = "100"		# All fans to full speed on power up
							register "fan1_duty" = "100"			# Fan 1 to full speed
							register "fan2_duty" = "100"			# Fan 2 to full speed
							register "fan3_duty" = "100"			# Fan 3 to full speed
							register "fan4_duty" = "100"			# Fan 4 to full speed
							register "fan5_duty" = "100"			# Fan 5 to full speed
							register "fan6_duty" = "100"			# Fan 6 to full speed
							register "fan7_duty" = "100"			# Fan 7 to full speed
							register "fan8_duty" = "100"			# Fan 8 to full speed
							register "vcore1_high_limit_mv" = "1500"	# VCORE1 (Node 0) high limit to 1.5V
							register "vcore1_low_limit_mv" = "900"		# VCORE1 (Node 0) low limit to 0.9V
							register "vcore2_high_limit_mv" = "1500"	# VCORE2 (Node 1) high limit to 1.5V
							register "vcore2_low_limit_mv" = "900"		# VCORE2 (Node 1) low limit to 0.9V
							register "vsen3_high_limit_mv" = "1600"		# VSEN1 (Node 0 RAM voltage) high limit to 1.6V
							register "vsen3_low_limit_mv" = "1100"		# VSEN1 (Node 0 RAM voltage) low limit to 1.1V
							register "vsen4_high_limit_mv" = "1600"		# VSEN2 (Node 1 RAM voltage) high limit to 1.6V
							register "vsen4_low_limit_mv" = "1100"		# VSEN2 (Node 1 RAM voltage) low limit to 1.1V
							register "vsen5_high_limit_mv" = "1250"		# VSEN5 (Node 0 HT link voltage) high limit to 1.25V
							register "vsen5_low_limit_mv" = "1150"		# VSEN5 (Node 0 HT link voltage) low limit to 1.15V
							register "vsen6_high_limit_mv" = "1250"		# VSEN6 (Node 1 HT link voltage) high limit to 1.25V
							register "vsen6_low_limit_mv" = "1150"		# VSEN6 (Node 1 HT link voltage) low limit to 1.15V
							register "vsen7_high_limit_mv" = "1250"		# VSEN7 (Northbridge core voltage) high limit to 1.25V
							register "vsen7_low_limit_mv" = "1050"		# VSEN7 (Northbridge core voltage) low limit to 1.05V
							register "vsen8_high_limit_mv" = "1900"		# VSEN8 (+1.8V) high limit to 1.9V
							register "vsen8_low_limit_mv" = "1700"		# VSEN8 (+1.8V) low limit to 1.7V
							register "vsen9_high_limit_mv" = "1250"		# VSEN9 (+1.2V) high limit to 1.25V
							register "vsen9_low_limit_mv" = "1150"		# VSEN9 (+1.2V) low limit to 1.15V
							register "vsen10_high_limit_mv" = "1150"	# VSEN10 (+1.1V) high limit to 1.15V
							register "vsen10_low_limit_mv" = "1050"		# VSEN10 (+1.1V) low limit to 1.05V
							register "vsen11_high_limit_mv" = "1625"	# VSEN11 (5VSB, scaling factor ~3.2) high limit to 5.2V
							register "vsen11_low_limit_mv" = "1500"		# VSEN11 (5VSB, scaling factor ~3.2) low limit to 4.8V
							register "vsen12_high_limit_mv" = "1083"	# VSEN12 (+12V, scaling factor ~12) high limit to 13V
							register "vsen12_low_limit_mv" = "917"		# VSEN12 (+12V, scaling factor ~12) low limit to 11V
							register "vsen13_high_limit_mv" = "1625"	# VSEN13 (+5V, scaling factor ~3.2) high limit to 5.2V
							register "vsen13_low_limit_mv" = "1500"		# VSEN13 (+5V, scaling factor ~3.2) low limit to 4.8V
							register "vdd_high_limit_mv" = "3500"		# 3VDD high limit to 3.5V
							register "vdd_low_limit_mv" = "3100"		# 3VDD low limit to 3.1V
							register "vsb_high_limit_mv" = "3500"		# 3VSB high limit to 3.5V
							register "vsb_low_limit_mv" = "3100"		# 3VSB low limit to 3.1V
							register "vbat_high_limit_mv" = "3500"		# VBAT (+3V) high limit to 3.5V
							register "vbat_low_limit_mv" = "2500"		# VBAT (+3V) low limit to 2.5V
							register "smbus_aux" = "1"			# Device located on auxiliary SMBUS controller
							device i2c 0x2f on end
						end
					end
					device pci 14.1 on end			# IDE 0x439c
					device pci 14.2 on end			# HDA 0x4383 (ASUS MIO add-on card)
					device pci 14.3 on			# LPC 0x439d (SMBUS primary controller)
						chip superio/winbond/w83667hg-a	# Super I/O
							device pnp 2e.0 off end		# FDC; Not available on the KGPE-D16
							device pnp 2e.1 off end		# LPT1; Not available on the KGPE-D16
							device pnp 2e.2 on		# COM1
								io 0x60 = 0x3f8
								irq 0x70 = 4
							end
							device pnp 2e.3 on		# COM2
								io 0x60 = 0x2f8
								irq 0x70 = 3
							end
							device pnp 2e.5 on		# PS/2 keyboard & mouse
								io 0x60 = 0x60
								io 0x62 = 0x64
								irq 0x70 = 1
								irq 0x72 = 12
							end
							device pnp 2e.106 off end	# SPI: Not available on the KGPE-D16
							device pnp 2e.107 off end	# GIPO6
							device pnp 2e.207 off end	# GIPO7
							device pnp 2e.307 off end	# GIPO8
							device pnp 2e.407 off end	# GIPO9
							device pnp 2e.8 off end		# WDT
							device pnp 2e.108 off end	# GPIO 1
							device pnp 2e.9 off end		# GPIO2
							device pnp 2e.109 off end	# GPIO3
							device pnp 2e.209 off end	# GPIO4
							device pnp 2e.309 off end	# GPIO5
							device pnp 2e.a on end		# ACPI
							device pnp 2e.b on		# HW Monitor
								io 0x60 = 0x290
								# IRQ purposefully not assigned to prevent lockups
							end
							device pnp 2e.c off end		# PECI
							device pnp 2e.d off end		# VID_BUSSEL
							device pnp 2e.f off end		# GPIO_PP_OD
						end
						chip drivers/pc80/tpm
							device pnp 4e.0 on end		# TPM module
						end
					end
					device pci 14.4 on			# Bridge
						device pci 1.0 on end		# VGA
						device pci 2.0 on end		# FireWire
						device pci 3.0 on		# Slot
							# Slot			# PCI 0
						end
					end
					device pci 14.5 on end			# USB OHCI2 0x4399
				end
			end
			device pci 18.1 on end
			device pci 18.2 on end
			device pci 18.3 on end
			device pci 18.4 on end
			device pci 18.5 on end
			device pci 19.0 on end		# Socket 0 node 1
			device pci 19.1 on end
			device pci 19.2 on end
			device pci 19.3 on end
			device pci 19.4 on end
			device pci 19.5 on end
			device pci 1a.0 on end		# Socket 1 node 0
			device pci 1a.1 on end
			device pci 1a.2 on end
			device pci 1a.3 on end
			device pci 1a.4 on end
			device pci 1a.5 on end
			device pci 1b.0 on end		# Socket 1 node 1
			device pci 1b.1 on end
			device pci 1b.2 on end
			device pci 1b.3 on end
			device pci 1b.4 on end
			device pci 1b.5 on end
		end
	end
end