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SPD mux
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DIMM_A1 SDA signal traced to U6 pin 1
Destructive testing of failed board (removal of U7 northbridge!) yielded the following information:
U6 S0 <--> U7 W2
U6 S1 <--> U7 W3

Proprietary BIOS enables the SPD during POST with:
S0: LOW
S1: LOW

then temporarily switches to:
S0: LOW
S1: HIGH

then switches to runtime mode with:
S0: HIGH
S1: LOW

After probing with a custom GPIO-flipping tool under Linux the following GPIO mappings were found:
CK804 pin W2 <--> GPIO43
CK804 pin W3 <--> GPIO44

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W83793 (U46)
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Sensor mappings:
FRNT_FAN1: FAN3
FRNT_FAN2: FAN4
FRNT_FAN3: FAN5
FRNT_FAN4: FAN6
FRNT_FAN5: FAN9
FRNT_FAN6: FAN10
REAR_FAN1: FAN7
REAR_FAN2: FAN8
REAR_FAN3: FAN11
REAR_FAN4: FAN12

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Other hardware
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Power LED (-) is connected to U15 (SuperIO) pin 64 via U4 pins 5,6 and a small MOSFET
ID LED (-) is connected to a ??? via U4 pins 1,2,3,4 and U77 pins 5,6
It appears that setting U15 (SuperIO) pin 88 LOW will override the ID LED and force it ON

PCIe slot WAKE# connects to U7 pin E23 (PCIE_WAKE#)

CPU_WARN1 is driven by (???) via a simple buffer (U13 pin 10)
MEM_WARN1 is driven by U7 pin AD3 (CPUVDD_EN) via a simple buffer (U101 pin 3)

U7 pin AK3 is disconnected (routed to unpopulated capacitor/resistor)
PU1 pin 37 (VDDPWRGD) drives U7 pin AJ4 (CPU_VLD)
A small MOSFET directly above another small MOSFET directly above the right-hand edge of the PCIe slot drives U7 pin AK5 (HT_VLD)

When > Barcelona CPU installed on PCB rev 1.04G:
U7 pin AK4 (MEM_VLD): HIGH
PU1 pin 37:           LOW
U7 pin AK5:           LOW

HyperTransport 1.2V supply appears to be generated by a linear regulator containing Q191 and downconverting the CK804 1.5V supply
The enable pin appears to be tied to AUX_PANEL pin 1 (+5VSB) via a resistor
Through two MOSFETs the HT supply enable pin is tied to U7 pin AE3 (HTVDD_EN)