##
## This file is part of the LinuxBIOS project.
##
## Copyright (C) 2007 AMD 
## (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
## Copyright (C) 2007 Philipp Degler <pdegler@rumms.uni-mannheim.de>
## (Thanks to LSRA University of Mannheim for their support)
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; either version 2 of the License, or
## (at your option) any later version.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
##

##
## Compute the location and size of where this firmware image
## (linuxBIOS plus bootloader) will live in the boot rom chip.
##
if USE_FAILOVER_IMAGE
        default ROM_SECTION_SIZE   = FAILOVER_SIZE
        default ROM_SECTION_OFFSET = ( ROM_SIZE - FAILOVER_SIZE )
else
    if USE_FALLBACK_IMAGE
        default ROM_SECTION_SIZE   = FALLBACK_SIZE
        default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
    else
        default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
        default ROM_SECTION_OFFSET = 0
    end
end

##
## Compute the start location and size size of
## The linuxBIOS bootloader.
##
default PAYLOAD_SIZE             = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
default CONFIG_ROM_PAYLOAD_START = ( 0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1 )

##
## Compute where this copy of linuxBIOS will start in the boot rom
##
default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )

##
## Compute a range of ROM that can cached to speed up linuxBIOS,
## execution speed.
##
## XIP_ROM_SIZE must be a power of 2.  (here 64 Kbyte)
## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
##
default XIP_ROM_SIZE = ( 64 * 1024 )

if USE_FAILOVER_IMAGE
        default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE )
else
    if USE_FALLBACK_IMAGE
        default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE )
    else
        default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE )
    end
end

arch i386 end

##
## Build the objects we have code for in this directory.
##

driver mainboard.o

#dir /drivers/ati/ragexl

# Needed by irq_tables and mptable and acpi_tables.
object get_bus_conf.o

if HAVE_MP_TABLE
	object mptable.o
end

if HAVE_PIRQ_TABLE
	object irq_tables.o
end

if USE_DCACHE_RAM
	if CONFIG_USE_INIT
		makerule ./auto.o
			depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
			action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
		end
	else
		makerule ./auto.inc
			depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
			action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
			action "perl -e 's/.rodata/.rom.data/g' -pi $@"
			action "perl -e 's/.text/.section .rom.text/g' -pi $@"
		end
	end
end

##
## Build our 16 bit and 32 bit linuxBIOS entry code
##
if HAVE_FAILOVER_BOOT
    if USE_FAILOVER_IMAGE
        mainboardinit cpu/x86/16bit/entry16.inc
        ldscript /cpu/x86/16bit/entry16.lds
    end
else
    if USE_FALLBACK_IMAGE
        mainboardinit cpu/x86/16bit/entry16.inc
        ldscript /cpu/x86/16bit/entry16.lds
    end
end

mainboardinit cpu/x86/32bit/entry32.inc

if USE_DCACHE_RAM
        if CONFIG_USE_INIT
                ldscript /cpu/x86/32bit/entry32.lds
        end

        if CONFIG_USE_INIT
                ldscript /cpu/amd/car/cache_as_ram.lds
        end
end

##
## Build our reset vector (This is where linuxBIOS is entered)
##
if HAVE_FAILOVER_BOOT
    if USE_FAILOVER_IMAGE
        mainboardinit cpu/x86/16bit/reset16.inc
        ldscript /cpu/x86/16bit/reset16.lds
    else
        mainboardinit cpu/x86/32bit/reset32.inc
        ldscript /cpu/x86/32bit/reset32.lds
    end
else
    if USE_FALLBACK_IMAGE
        mainboardinit cpu/x86/16bit/reset16.inc
        ldscript /cpu/x86/16bit/reset16.lds
    else
        mainboardinit cpu/x86/32bit/reset32.inc
        ldscript /cpu/x86/32bit/reset32.lds
    end
end

if USE_DCACHE_RAM
else
	### Should this be in the northbridge code?
	mainboardinit arch/i386/lib/cpu_reset.inc
end

##
## Include an id string (For safe flashing)
##
mainboardinit southbridge/nvidia/ck804/id.inc
ldscript /southbridge/nvidia/ck804/id.lds

##
## ROMSTRAP table for CK804
##
if HAVE_FAILOVER_BOOT
	if USE_FAILOVER_IMAGE
		mainboardinit southbridge/nvidia/ck804/romstrap.inc
		ldscript /southbridge/nvidia/ck804/romstrap.lds
	end
else
	if USE_FALLBACK_IMAGE
		mainboardinit southbridge/nvidia/ck804/romstrap.inc
		ldscript /southbridge/nvidia/ck804/romstrap.lds
	end
end

if USE_DCACHE_RAM
	##
	## Setup Cache-As-Ram
	##
	mainboardinit cpu/amd/car/cache_as_ram.inc
end


###
### This is the early phase of linuxBIOS startup
### Things are delicate and we test to see if we should
### failover to another image.
###
if HAVE_FAILOVER_BOOT
    if USE_FAILOVER_IMAGE
        if USE_DCACHE_RAM
                ldscript /arch/i386/lib/failover_failover.lds
        end
    end
else
    if USE_FALLBACK_IMAGE
        if USE_DCACHE_RAM
                ldscript /arch/i386/lib/failover.lds
        end
    end
end

###
### O.k. We aren't just an intermediary anymore!
###

##
## Setup RAM
##
if USE_DCACHE_RAM
	if CONFIG_USE_INIT
		initobject auto.o
	else
		mainboardinit ./auto.inc
	end
end

##
## Include the secondary configuration files
##
if CONFIG_CHIP_NAME
	config chip.h
end

chip northbridge/amd/amdk8/root_complex
	device apic_cluster 0 on
		chip cpu/amd/socket_939
			device apic 0 on end
		end
	end

	device pci_domain 0 on
		chip northbridge/amd/amdk8 # mc0
			device pci 18.0 on # northbridge
				# Devices on link 0, link 0 == LDT 0
				chip southbridge/nvidia/ck804
					device pci 0.0 on end # HT
					device pci 1.0 on # LPC
						chip superio/ite/it8712f
							device pnp 2e.0 off # Floppy
								io 0x60 = 0x03f0
								irq 0x70 = 6
								drq 0x74 = 2
							end
							device pnp 2e.1 on # Com1
								io 0x60 = 0x03f8
								irq 0x70 = 4
							end
							device pnp 2e.2 off # Com2
								io 0x60 = 0x02f8
								irq 0x70 = 3
							end
							device pnp 2e.3 on # Parallel Port
								io 0x60 = 0x0378
								irq 0x70 = 7
							end
							device pnp 2e.4 on # Environment Controller
								io 0x60 = 0x0290
								io 0x62 = 0x0000
								irq 0x70 = 0x00
							end
							device pnp 2e.5 on # Keyboard
								io 0x60 = 0x0060
								io 0x62 = 0x0064
								irq 0x70 = 0x01
								irq 0x71 = 0x02
							end
							device pnp 2e.6 on # Mouse
								irq 0x70 = 0x0c
								irq 0x71 = 0x02
							end
							device pnp 2e.7 on # GPIO config
								# Set GPIO 1 & 2
								io 0x25 = 0x0000
								# Set GPIO 3 & 4
								io 0x27 = 0x2540
								# GPIO Polarity for Set 3
								io 0xb2 = 0x2100
								# GPIO Pin Internal Pull up for Set 3
								io 0xba = 0x0100
								# Simple I/O register config
								io 0xc0 = 0x0000
								io 0xc2 = 0x2540
								io 0xc8 = 0x0000
								io 0xca = 0x0500
							end
							device pnp 2e.8 off end # Midi port
							device pnp 2e.9 off end # Game port
							device pnp 2e.a off end # IR
						end
					end
					device pci 1.1 on # SM 0
						# chip drivers/generic/generic #dimm 0-0-0
						# 	device i2c 50 on end
						# end
						# chip drivers/generic/generic #dimm 0-0-1
						# 	device i2c 51 on end
						# end
						# chip drivers/generic/generic #dimm 0-1-0
						# 	device i2c 52 on end
						# end
						# chip drivers/generic/generic #dimm 0-1-1
						# 	device i2c 53 on end
						# end
						# chip drivers/generic/generic #dimm 1-0-0
						# 	device i2c 54 on end
						# end
						# chip drivers/generic/generic #dimm 1-0-1
						# 	device i2c 55 on end
						# end
						# chip drivers/generic/generic #dimm 1-1-0
						# 	device i2c 56 on end
						# end
						# chip drivers/generic/generic #dimm 1-1-1
						# 	device i2c 57 on end
						# end
					end # SM
					device pci 2.0 on end # USB 1.1
					device pci 2.1 on end # USB 2
					device pci 4.0 off end # ACI
					device pci 4.1 off end # MCI
					device pci 6.0 on end # IDE
					device pci 7.0 on end # SATA 1
					device pci 8.0 on end # SATA 0
					device pci 9.0 on end # PCI
					device pci a.0 on end # NIC
					device pci b.0 on end # PCI E 3
					device pci c.0 on end # PCI E 2
					device pci d.0 on end # PCI E 1
					device pci e.0 on end # PCI E 0
					register "ide0_enable" = "1"
					register "ide1_enable" = "1"
					register "sata0_enable" = "1"
					register "sata1_enable" = "1"
#					register "mac_eeprom_smbus" = "3"
#					register "mac_eeprom_addr" = "0x51"
				end

			end # device pci 18.0
			device pci 18.1 on end
			device pci 18.2 on end
			device pci 18.3 on end
		end # mc0
	end # pci_domain
end # root_complex