/*============================================================================ Copyright 2005 ADVANCED MICRO DEVICES, INC. All Rights Reserved. This software and any related documentation (the "Materials") are the confidential proprietary information of AMD. Unless otherwise provided in a software agreement specifically licensing the Materials, the Materials are provided in confidence and may not be distributed, modified, or reproduced in whole or in part by any means. LIMITATION OF LIABILITY: THE MATERIALS ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OF OR INABILITY TO USE THE MATERIALS, EVEN IF AMD HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, THE ABOVE LIMITATION MAY NOT APPLY TO YOU. AMD does not assume any responsibility for any errors which may appear in the Materials nor any responsibility to support or update the Materials. AMD retains the right to modify the Materials at any time, without notice, and is not obligated to provide such modified Materials to you. NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any further information, software, technical information, know-how, or show-how available to you. U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is subject to the restrictions as set forth in FAR 52.227-14 and DFAR 252.227-7013, et seq., or its successor. Use of the Materials by the Government constitutes acknowledgement of AMD's proprietary rights in them. ============================================================================*/ /* * 2005.9 yhlu modify that to more dynamic for AMD Opteron Based MB */ #include #include #include #include #include #include #include #define DUMP_ACPI_TABLES 1 #if DUMP_ACPI_TABLES == 1 static void dump_mem(unsigned start, unsigned end) { unsigned i; print_debug("dump_mem:"); for(i=start;i= 1 extern unsigned char AmlCode_ssdt2[]; //extern unsigned char AmlCode_ssdt3[]; //extern unsigned char AmlCode_ssdt4[]; //extern unsigned char AmlCode_ssdt5[]; //extern unsigned char AmlCode_ssdt6[]; //extern unsigned char AmlCode_ssdt7[]; //extern unsigned char AmlCode_ssdt8[]; #endif #define IO_APIC_ADDR 0xfec00000UL extern unsigned char bus_isa; extern unsigned char bus_8132_0; extern unsigned char bus_8132_1; extern unsigned char bus_8132_2; extern unsigned char bus_8111_0; extern unsigned char bus_8111_1; extern unsigned char bus_8151_0; extern unsigned char bus_8151_1; extern unsigned apicid_8111; extern unsigned apicid_8132_1; extern unsigned apicid_8132_2; extern unsigned pci1234[]; extern unsigned hc_possible_num; extern unsigned sblk; extern unsigned sbdn; unsigned long acpi_fill_madt(unsigned long current) { unsigned int gsi_base=0x18; /* create all subtables for processors */ current = acpi_create_madt_lapics(current); /* Write 8111 IOAPIC */ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, apicid_8111, IO_APIC_ADDR, 0); /* Write all 8131 IOAPICs */ { device_t dev; struct resource *res; dev = dev_find_slot(bus_8132_0, PCI_DEVFN(0x1,1)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, apicid_8132_1, res->base, gsi_base ); gsi_base+=7; } } dev = dev_find_slot(bus_8132_0, PCI_DEVFN(0x2,1)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, apicid_8132_2, res->base, gsi_base ); gsi_base+=7; } } } current += acpi_create_madt_irqoverride( (acpi_madt_irqoverride_t *) current, 0, 0, 2, 5 ); /* 0: mean bus 0--->ISA */ /* 0: PIC 0 */ /* 2: APIC 2 */ /* 5 mean: 0101 --> Edige-triggered, Active high*/ /* create all subtables for processors */ current = acpi_create_madt_lapic_nmis(current, 5, 1); /* 1: LINT1 connect to NMI */ return current; } //FIXME: next could be moved to northbridge/amd/amdk8/amdk8_acpi.c or cpu/amd/k8/k8_acpi.c begin static void int_to_stream(uint32_t val, uint8_t *dest) { int i; for(i=0;i<4;i++) { *(dest+i) = (val >> (8*i)) & 0xff; } } extern void get_bus_conf(void); static void update_ssdt(void *ssdt) { uint8_t *BUSN; uint8_t *MMIO; uint8_t *PCIO; uint8_t *SBLK; uint8_t *TOM1; uint8_t *HCLK; uint8_t *SBDN; int i; device_t dev; uint32_t dword; msr_t msr; BUSN = ssdt+0x3a; //+5 will be next BUSN MMIO = ssdt+0x57; //+5 will be next MMIO PCIO = ssdt+0xaf; //+5 will be next PCIO SBLK = ssdt+0xdc; // one byte TOM1 = ssdt+0xe3; // HCLK = ssdt+0xfa; //+5 will be next HCLK SBDN = ssdt+0xed;// dev = dev_find_slot(0, PCI_DEVFN(0x18, 1)); for(i=0;i<4;i++) { dword = pci_read_config32(dev, 0xe0+i*4); int_to_stream(dword, BUSN+i*5); } for(i=0;i<0x10;i++) { dword = pci_read_config32(dev, 0x80+i*4); int_to_stream(dword, MMIO+i*5); } for(i=0;i<0x08;i++) { dword = pci_read_config32(dev, 0xc0+i*4); int_to_stream(dword, PCIO+i*5); } get_bus_conf(); //it will get sblk, pci1234, and sbdn *SBLK = (uint8_t)(sblk); msr = rdmsr(TOP_MEM); int_to_stream(msr.lo, TOM1); for(i=0;iheader.length; acpi_add_table(rsdt,madt); /* SRAT */ printk_debug("ACPI: * SRAT\n"); srat = (acpi_srat_t *) current; acpi_create_srat(srat); current+=srat->header.length; acpi_add_table(rsdt,srat); /* SSDT */ printk_debug("ACPI: * SSDT\n"); ssdt = (acpi_header_t *)current; current += ((acpi_header_t *)AmlCode_ssdt)->length; memcpy((void *)ssdt, (void *)AmlCode_ssdt, ((acpi_header_t *)AmlCode_ssdt)->length); //Here you need to set value in pci1234, sblk and sbdn in get_bus_conf.c update_ssdt((void*)ssdt); /* recalculate checksum */ ssdt->checksum = 0; ssdt->checksum = acpi_checksum((unsigned char *)ssdt,ssdt->length); acpi_add_table(rsdt,ssdt); #if ACPI_SSDTX_NUM >= 1 // we need to make ssdt2 match to PCI2 in pci2.asl,... pci1234[1] AmlCode_ssdtx[1] = AmlCode_ssdt2; // AmlCode_ssdtx[2] = AmlCode_ssdt3; // AmlCode_ssdtx[3] = AmlCode_ssdt4; // AmlCode_ssdtx[4] = AmlCode_ssdt5; // AmlCode_ssdtx[5] = AmlCode_ssdt6; // AmlCode_ssdtx[6] = AmlCode_ssdt7; // AmlCode_ssdtx[7] = AmlCode_ssdt8; //same htio, but different possition? We may have to copy, change HCIN, and recalculate the checknum and add_table for(i=1;ilength; memcpy((void *)ssdtx, (void *)AmlCode_ssdtx[i], ((acpi_header_t *)AmlCode_ssdtx[i])->length); acpi_add_table(rsdt,ssdtx); } #endif /* FACS */ printk_debug("ACPI: * FACS\n"); facs = (acpi_facs_t *) current; current += sizeof(acpi_facs_t); acpi_create_facs(facs); /* DSDT */ printk_debug("ACPI: * DSDT\n"); dsdt = (acpi_header_t *)current; current += ((acpi_header_t *)AmlCode)->length; memcpy((void *)dsdt,(void *)AmlCode, \ ((acpi_header_t *)AmlCode)->length); printk_debug("ACPI: * DSDT @ %08x Length %x\n",dsdt,dsdt->length); /* FDAT */ printk_debug("ACPI: * FADT\n"); fadt = (acpi_fadt_t *) current; current += sizeof(acpi_fadt_t); acpi_create_fadt(fadt,facs,dsdt); acpi_add_table(rsdt,fadt); #if DUMP_ACPI_TABLES == 1 printk_debug("rsdp\n"); dump_mem(rsdp, ((void *)rsdp) + sizeof(acpi_rsdp_t)); printk_debug("rsdt\n"); dump_mem(rsdt, ((void *)rsdt) + sizeof(acpi_rsdt_t)); printk_debug("madt\n"); dump_mem(madt, ((void *)madt) + madt->header.length); printk_debug("srat\n"); dump_mem(srat, ((void *)srat) + srat->header.length); printk_debug("ssdt\n"); dump_mem(ssdt, ((void *)ssdt) + ssdt->length); printk_debug("fadt\n"); dump_mem(fadt, ((void *)fadt) + fadt->header.length); #endif printk_info("ACPI: done.\n"); return current; }