# SPDX-License-Identifier: GPL-2.0-only config PLATFORM_USES_FSP2_0 bool default n help Include FSP 2.0 wrappers and functionality config PLATFORM_USES_FSP2_1 bool default n select PLATFORM_USES_FSP2_0 select FSP_USES_CB_STACK select FSP_PEIM_TO_PEIM_INTERFACE help Include FSP 2.1 wrappers and functionality. Features added into FSP 2.1 specification that impacts coreboot are: 1. Remove FSP stack switch and use the same stack with boot firmware 2. FSP should support external PPI interface pulled in via FSP_PEIM_TO_PEIM_INTERFACE config PLATFORM_USES_FSP2_2 bool default n select PLATFORM_USES_FSP2_1 help Include FSP 2.2 wrappers and functionality. Features added into FSP 2.2 specification that impact coreboot are: 1. Added multi-phase silicon initialization to increase the modularity of the FspSiliconInit() API 2. FSP_INFO_HEADER changes to add FspMultiPhaseSiInitEntryOffset 3. Added EnableMultiPhaseSiliconInit, bootloaders designed for FSP2.0/2.1 can disable the FspMultiPhaseSiInit() API and continue to use FspSiliconInit() without change. if PLATFORM_USES_FSP2_0 config HAVE_INTEL_FSP_REPO bool help Select this, if the FSP binaries for the platform are public and available in 3rdparty/fsp/. When selecting this option, the platform must also set FSP_HEADER_PATH and FSP_FD_PATH correctly. config FSP_USE_REPO bool "Use binaries of the Intel FSP repository on GitHub" depends on HAVE_INTEL_FSP_REPO default y help Select this option to use the default FSP headers and binaries found in the IntelFsp GitHub repository at https://github.com/IntelFsp/FSP/ If unsure, say Y. config FSP_HEADER_PATH string "Location of FSP headers" if !FSP_USE_REPO help Include directory with the FSP ABI header files. config FSP_FD_PATH string depends on FSP_USE_REPO help Path to the FSP FD file that contains the individual FSP-T, FSP-M and FSP-S binaries. config ADD_FSP_BINARIES bool "Add Intel FSP 2.0 binaries to CBFS" if !FSP_USE_REPO default y if FSP_USE_REPO help Add the FSP-M and FSP-S binaries to CBFS. config FSP_T_CBFS string "Name of FSP-T in CBFS" depends on FSP_CAR default "fspt.bin" config FSP_S_CBFS string "Name of FSP-S in CBFS" default "fsps.bin" config FSP_M_CBFS string "Name of FSP-M in CBFS" default "fspm.bin" config FSP_T_FILE string "Intel FSP-T (temp RAM init) binary path and filename" if !FSP_USE_REPO depends on ADD_FSP_BINARIES depends on FSP_CAR default "\$(obj)/Fsp_T.fd" if FSP_USE_REPO help The path and filename of the Intel FSP-T binary for this platform. config FSP_M_FILE string "Intel FSP-M (memory init) binary path and filename" if !FSP_USE_REPO depends on ADD_FSP_BINARIES default "\$(obj)/Fsp_M.fd" if FSP_USE_REPO help The path and filename of the Intel FSP-M binary for this platform. config FSP_S_FILE string "Intel FSP-S (silicon init) binary path and filename" if !FSP_USE_REPO depends on ADD_FSP_BINARIES default "\$(obj)/Fsp_S.fd" if FSP_USE_REPO help The path and filename of the Intel FSP-S binary for this platform. config FSP_CAR bool default n help Use FSP APIs to initialize & Tear Down the Cache-As-Ram config FSP_M_XIP bool default n help Select this value when FSP-M is execute-in-place. config FSP_T_XIP bool default n help Select this value when FSP-T is execute-in-place. config FSP_USES_CB_STACK bool default n help Enable support for fsp to use same stack as coreboot. This option allows fsp to continue using coreboot stack without reinitializing stack pointer. This feature is supported Icelake onwards. config FSP_TEMP_RAM_SIZE hex depends on FSP_USES_CB_STACK help The amount of anticipated heap usage in CAR by FSP to setup HOB. This configuration is applicable for FSP specification using shared stack with coreboot/bootloader. Sync this value with Platform FSP integration guide recommendation. config FSP2_0_USES_TPM_MRC_HASH bool depends on TPM1 || TPM2 depends on VBOOT && VBOOT_STARTS_IN_BOOTBLOCK default y if HAS_RECOVERY_MRC_CACHE default n select VBOOT_HAS_REC_HASH_SPACE help Store hash of trained recovery MRC cache in NVRAM space in TPM. Use the hash to validate recovery MRC cache before using it. This hash needs to be updated every time recovery mode training is recomputed, or if the hash does not match recovery MRC cache. Selecting this option requires that TPM already be setup by this point in time. Thus it is only compatible when the option VBOOT_STARTS_IN_BOOTBLOCK is selected, which causes verstage and TPM setup to occur prior to memory initialization. config FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS bool help This is selected by SoC or mainboard to supply their own concept of a version for the memory settings respectively. This allows deployed systems to bump their version number with the same FSP which will trigger a retrain of the memory. config FSP_PEIM_TO_PEIM_INTERFACE bool select FSP_USES_MP_SERVICES_PPI help This option allows SOC user to create specific PPI for Intel FSP usage, coreboot will provide required PPI structure definitions along with all APIs as per EFI specification. So far this feature is limited till EFI_PEI_MP_SERVICE_PPI and this option might be useful to add further PPI if required. config HAVE_FSP_LOGO_SUPPORT bool default n config FSP2_0_DISPLAY_LOGO bool "Enable logo" default n depends on HAVE_FSP_LOGO_SUPPORT help Uses the FSP to display the boot logo. This method supports a BMP file only. The uncompressed size can be up to 1 MB. The logo can be compressed using LZMA. config FSP2_0_LOGO_FILE_NAME string "Logo file" depends on FSP2_0_DISPLAY_LOGO default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/logo.bmp" config FSP_COMPRESS_FSP_S_LZMA bool config FSP_COMPRESS_FSP_S_LZ4 bool config FSP_COMPRESS_FSP_M_LZMA bool depends on !FSP_M_XIP config FSP_COMPRESS_FSP_M_LZ4 bool depends on !FSP_M_XIP config FSP_M_ADDR hex help The address FSP-M will be relocated to during build time if FSP_PEIM_TO_PEIM_INTERFACE source "src/drivers/intel/fsp2_0/ppi/Kconfig" endif endif