##
## This file is part of the coreboot project.
##
## Copyright (C) 2014 Sage Electronic Engineering, LLC.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc.
##

config PLATFORM_USES_FSP1_1
	bool
	help
	  Does the code require the Intel Firmware Support Package?

if PLATFORM_USES_FSP1_1

comment "Intel FSP 1.1"

config DCACHE_RAM_BASE
	hex
	default 0xfef00000

config DCACHE_RAM_SIZE
	hex
	default 0x4000

config HAVE_FSP_BIN
	bool "Should the Intel FSP binary be added to the flash image"
	help
	  Select this option to add an Intel FSP binary to
	  the resulting coreboot image.

	  Note: Without this binary, coreboot builds relying on the FSP
	  will not boot

if HAVE_FSP_BIN

config CPU_MICROCODE_CBFS_LEN
	hex "Microcode update region length in bytes"
	default 0
	help
	  The length in bytes of the microcode update region.

config CPU_MICROCODE_CBFS_LOC
	hex "Microcode update base address in CBFS"
	default 0
	help
	  The location (base address) in CBFS that contains the microcode update
	  binary.

config FSP_FILE
	string "Intel FSP binary path and filename"
	help
	  The path and filename of the Intel FSP binary for this platform.

config FSP_IMAGE_ID_DWORD0
	hex "First 4 bytes of 8 byte platform string"
	help
	  The first four bytes of the eight byte platform specific string
	  used to identify the FSP binary that should be used.

config FSP_IMAGE_ID_DWORD1
	hex "Second 4 bytes of 8 byte platform string"
	help
	  The second four bytes of the eight byte platform specific string
	  used to identify the FSP binary that should be used.

config FSP_INCLUDE_PATH
	string "Path for FSP specific include files"
	help
	  The path and filename of the Intel FSP binary for this platform.

config FSP_LOC
	hex "Intel FSP Binary location in CBFS"
	help
	  The location in CBFS that the FSP is located. This must match the
	  value that is set in the FSP binary.  If the FSP needs to be moved,
	  rebase the FSP with Intel's BCT (tool).

endif #HAVE_FSP_BIN

config CACHE_ROM_SIZE_OVERRIDE
	hex "Cache ROM Size"
	default CBFS_SIZE
	help
	  This is the size of the cachable area that is passed into the FSP in
	  the early initialization.  Typically this should be the size of the
	  CBFS area, but the size must be a power of 2 whereas the CBFS size
	  does not have this limitation.

config DISPLAY_FAST_BOOT_DATA
	bool "Display fast boot data"
	default n

config DISPLAY_HOBS
	bool "Display hand-off-blocks (HOBs)"
	default n

config DISPLAY_VBT
	bool "Display Video BIOS Table (VBT)"
	default n

config DISPLAY_FSP_ENTRY_POINTS
	bool "Display FSP entry points"
	default n

config DISPLAY_UPD_DATA
	bool "Display UPD data"
	default n
	help
	  Display the user specified product data prior to memory
	  initialization.

config FSP_USES_UPD
	bool
	default n
	help
	  If this FSP uses UPD/VPD data regions, select this in the chipset
	  Kconfig.

config GOP_SUPPORT
	bool "Enable GOP support"
	default y

config USE_GENERIC_FSP_CAR_INC
	bool
	default n
	help
	  The chipset can select this to use a generic cache_as_ram.inc file
	  that should be good for all FSP based platforms.

config VBT_FILE
	string "GOP Video BIOS table binary path"
	depends on GOP_SUPPORT
	default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/vbt.bin"

endif #PLATFORM_USES_FSP1_1