##
## This file is part of the coreboot project.
##
## Copyright (C) 2013 DMP Electronics Inc.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc.
##

config CPU_DMP_VORTEX86EX
	bool

if CPU_DMP_VORTEX86EX

config CPU_SPECIFIC_OPTIONS
	def_bool y
	select ARCH_BOOTBLOCK_X86_32
	select ARCH_VERSTAGE_X86_32
	select ARCH_ROMSTAGE_X86_32
	select ARCH_RAMSTAGE_X86_32
	select UDELAY_TSC

# ROM Strap PLL config setting :

choice
	prompt "ROM Strap PLL config"
	default PLL_300_300_33

config PLL_200_200_33
	bool "CPU=200Mhz/DRAM=200Mhz/PCI=33Mhz"

config PLL_300_300_33
	bool "CPU=300Mhz/DRAM=300Mhz/PCI=33Mhz"

config PLL_300_300_100
	bool "CPU=300Mhz/DRAM=300Mhz/PCI=100Mhz"

config PLL_400_200_33
	bool "CPU=400Mhz/DRAM=200Mhz/PCI=33Mhz"

config PLL_400_200_100
	bool "CPU=400Mhz/DRAM=200Mhz/PCI=100Mhz"

config PLL_400_400_33
	bool "CPU=400Mhz/DRAM=400Mhz/PCI=33Mhz"

config PLL_500_250_33
	bool "CPU=500Mhz/DRAM=250Mhz/PCI=33Mhz"

config PLL_500_500_33
	bool "CPU=500Mhz/DRAM=500Mhz/PCI=33Mhz"

config PLL_400_300_33
	bool "CPU=400Mhz/DRAM=300Mhz/PCI=33Mhz"

config PLL_400_300_100
	bool "CPU=400Mhz/DRAM=300Mhz/PCI=100Mhz"

config PLL_444_333_33
	bool "CPU=444Mhz/DRAM=333Mhz/PCI=33Mhz"

config PLL_466_350_33
	bool "CPU=466Mhz/DRAM=350Mhz/PCI=33Mhz"

config PLL_500_375_33
	bool "CPU=500Mhz/DRAM=375Mhz/PCI=33Mhz"

endchoice

config CHIPSET_BOOTBLOCK_INCLUDE
	string
	default "cpu/dmp/vortex86ex/chipset_bootblock.inc"

endif