Intel® x86 coreboot/FSP Development Process

The x86 development process for coreboot is broken into the following components:

coreboot SoC development
coreboot mainboard development
FSP 1.1 integration

The development process has two main phases:

Minimal coreboot; This phase is single threaded
Adding coreboot features

Minimal coreboot

The combined steps below describe how to bring up a minimal coreboot for a system-on-a-chip (SoC) and a development board:

The initial coreboot steps are single threaded! The initial minimal FSP development is also single threaded. Progress can speed up by adding more developers after the minimal coreboot/FSP implementation reaches the payload.

Get the necessary tools:
- Linux: Use your package manager to install m4 bison flex and the libcurses development package.
  - Ubuntu or other Linux distribution that use apt, run:
```
sudo apt-get install m4 bison flex libncurses5-dev
```
Build the cross tools for i386:
- Linux:
```
make crossgcc-i386
```
  To use multiple processors for the toolchain build (which takes a long time), use:
```
make crossgcc-i386 CPUS=N
```
  where N is the number of cores to use for the build.
Get something to build:
1. FSP 1.1 required files
2. SoC required files
3. Board required files
Get result to start booting
Early Debug
Implement and debug the bootblock code
Implement and debug the call to TempRamInit
Enable the serial port
1. Power on, enable and configure GPIOs for the debug serial UART
2. Add the serial outupt support to romstage
Enable coreboot/FSP debugging
Determine the Previous Sleep State
Enable DRAM:
1. Implement the SoC MemoryInit Support
2. Implement the board support to read the Memory Timing Data

Features
SoC	Where	Testing
Cache-as-RAM	Find FSP binary: cache_as_ram.inc Enable: FSP 1.1 TempRamInit called from cache_as_ram.inc Disable: FSP 1.1 TempRamExit called from after_raminit.S	FindFSP: POST code 0x90 (POST_FSP_TEMP_RAM_INIT) is displayed Enable: POST code 0x2A is displayed Disable: CONFIG_DISPLAY_MTRRS=y, MTRRs displayed after call to TempRamExit
Board	Where	Testing
DRAM	Load SPD data: src/soc/mainboard/<Vendor>/<Board>/spd/spd.c UPD Setup: src/soc<Vendor>//<Chip Family>/romstage/romstage.c src/mainboard/<Vendor>/<Board>/romstage.c FSP 1.1 MemoryInit called from src/drivers/intel/fsp1_1/raminit.c	Select the following Kconfig values DISPLAY_HOBS DISPLAY_UPD_DATA Testing successful if: MemoryInit UPD values are correct MemoryInit returns 0 (success) and The the message "ERROR - coreboot's requirements not met by FSP binary!" is not displayed
Serial Port	SoC Support Enable: src/soc/mainboard/<Board>/com_init.c/car_mainboard_pre_console_init	Debug serial output works
FSP	Where	Testing
TempRamInit	FSP TempRamInit	FSP binary found: POST code 0x90 (POST_FSP_TEMP_RAM_INIT) is displayed TempRamInit successful: POST code 0x2A is displayed
MemoryInit	SoC support Board support	Select the following Kconfig values DISPLAY_HOBS DISPLAY_UPD_DATA Testing successful if: MemoryInit UPD values are correct MemoryInit returns 0 (success) and The the message "ERROR - coreboot's requirements not met by FSP binary!" is not displayed

Modified: 31 January 2016

Intel® x86 coreboot/FSP Development Process

Minimal coreboot

Features