x86 System on a Chip (SoC) Development

SoC development is best done in parallel with development for a specific board. The combined steps are listed here. The development steps for the SoC are listed below:

1. FSP 1.1 required files
2. SoC Required Files
3. Start Booting
4. Early Debug

Required Files

Create the directory as src/soc/<Vendor>/<Chip Family>.

The following files are required to build a new SoC:

• Include files
  • include/soc/pei_data.h
  • include/soc/pm.h
• Kconfig - Defines the Kconfig value for the SoC and selects the tool chains for the various stages:
  • select ARCH_BOOTBLOCK_<Tool Chain>
  • select ARCH_RAMSTAGE_<Tool Chain>
  • select ARCH_ROMSTAGE_<Tool Chain>
  • select ARCH_VERSTAGE_<Tool Chain>
• Makefile.inc - Specify the include paths
• memmap.c - Top of usable RAM

Start Booting

Some SoC parts require additional firmware components in the flash. This section describes how to add those pieces.

Intel Firmware Descriptor

The Intel Firmware Descriptor (IFD) is located at the base of the flash part. The following command overwrites the base of the flash image with the Intel Firmware Descriptor:

dd if=descriptor.bin of=build/coreboot.rom conv=notrunc >/dev/null 2>&1

Management Engine Binary

Some SoC parts contain and require that the Management Engine (ME) be running before it is possible to bring the x86 processor out of reset. A binary file containing the management engine code must be added to the firmware using the ifdtool. The following commands add this binary blob:

util/ifdtool/ifdtool -i ME:me.bin  build/coreboot.rom
mv build/coreboot.rom.new build/coreboot.rom

Early Debug

Early debugging between the reset vector and the time the serial port is enabled is most easily done by writing values to port 0x80.

Success

When the reset vector is successfully invoked, port 0x80 will output the following value:

• 0x01: POST_RESET_VECTOR_CORRECT - Bootblock successfully executed the reset vector and entered the 16-bit code at _start

Modified: 31 January 2016