x86 Board Development
Board development requires System-on-a-Chip (SoC) support.
The combined steps are listed
here.
The development steps for the board are listed below:
- Required Files
- Enable Serial Output
- Load the Memory Timing Data
- Disable the PCI devices
- ACPI Tables
Create the board directory as src/mainboard/<Vendor>/<Board>.
The following files are required to build a new board:
- Kconfig.name - Defines the Kconfig value for the board
- Kconfig
- Selects the SoC for the board and specifies the SPI flash size
- BOARD_ROMSIZE_KB_<Size>
- SOC_<Vendor>_<Chip Family>
- Declare the Kconfig values for:
- MAINBOARD_DIR
- MAINBOARD_PART_NUMBER
- MAINBOARD_VENDOR
- devicetree.cb - Enable root bridge and serial port
- The first line must be "chip soc/Intel/<soc family>";
this path is used by the generated static.c to include the chip.h
header file
- romstage.c
- Add routine mainboard_romstage_entry which calls romstage_common
- Configure coreboot build:
- Set LOCALVERSION
- FLASHMAP_OFFSET = 0x00700000
- Select vendor for the board
- Select the board
- CBFS_SIZE = 0x00100000
- Set the CPU_MICROCODE_CBFS_LEN
- Set the CPU_MICROCODE_CBFS_LOC
- Set the FSP_IMAGE_ID_STRING
- Set the FSP_LOC
- Disable GOP_SUPPORT
- No payload
- Choose the default value for all other options
Use the following steps to enable serial output:
- Implement the car_mainboard_pre_console_init routine in the com_init.c
file:
- Power on and enable the UART controller
- Connect the UART receive and transmit data lines to the
appropriate SoC pins
- Add Makefile.inc
- Add com_init.c to romstage
Memory timing data is located in the flash. This data is in the format of
serial presence detect
(SPD) data.
Use the following steps to load the SPD data:
- Edit Kconfig to add the DISPLAY_SPD_DATA" value which enables the
display of the SPD data being passed to MemoryInit
- Create an "spd" subdirectory
- Create an spd/spd.c file for the SPD implementation
- Implement the mainboard_fill_spd_data routine
- Read the SPD data either from the spd.bin file or using I2C or SMBUS
- Fill in the pei_data structure with SPD data for each of the DIMMs
- Set the DIMM channel configuration
- Add an .spd.hex file containing the memory timing data to the spd subdirectory
- Create spd/Makefile.inc
- Add spd.c to romstage
- Add the .spd.hex file to SPD_SOURCES
- Edit Makefile.inc to add the spd subdirectory
- Edit romstage.c
- Call mainboard_fill_spd_data
- Add mainboard_memory_init_params to copy the SPD and DRAM
configuration data from the pei_data structure into the UPDs
for MemoryInit
- Edit devicetree.cb
- Include the UPD parameters for MemoryInit except for:
- Address of SPD data
- DRAM configuration set above
- A working FSP
MemoryInit
routine is required to complete debugging
- Debug the result until port 0x80 outputs
- 0x34:
- Just after entering
raminit
- 0x36:
- Just before displaying the
UPD parameters
for FSP MemoryInit
- 0x92: POST_FSP_MEMORY_INIT
- Just before calling FSP
MemoryInit
- 0x37:
- Just after returning from FSP
MemoryInit
- Continue debugging with CONFIG_DISPLAY_HOBS enabled until TempRamExit is called
Ramstage's BS_DEV_ENUMERATE state displays the PCI vendor and device IDs for all
of the devices in the system. Edit the devicetree.cb file:
- Edit the devicetree.cb file:
- Add an entry for a PCI device.function and turn it off. The entry
should look similar to:
device pci 14.0 off end
- Turn on the devices for:
- Memory Controller
- Debug serial device
- Debug until the BS_DEV_ENUMERATE state shows the proper state for all of the devices
- Edit Kconfig
- Add "select HAVE_ACPI_TABLES"
- Add the acpi_tables.c module:
- Include soc/acpi.h
- Add the acpi_create_fadt routine
- fill in the ACPI header
- Call the acpi_fill_in_fadt routine
- Add the dsdt.asl module:
Modified: 20 February 2016