x86 Board Development

Board development requires System-on-a-Chip (SoC) support. The combined steps are listed here. The development steps for the board are listed below:

1. Required Files
2. Enable Serial Output
3. Load the Memory Timing Data
4. Disable the PCI devices

Required Files

Create the board directory as src/mainboard/<Vendor>/<Board>.

The following files are required to build a new board:

1. Kconfig.name - Defines the Kconfig value for the board
2. Kconfig
   1. Selects the SoC for the board and specifies the SPI flash size
      1. BOARD_ROMSIZE_KB_<Size>
      2. SOC_<Vendor>_<Chip Family>
   2. Declare the Kconfig values for:
      1. MAINBOARD_DIR
      2. MAINBOARD_PART_NUMBER
      3. MAINBOARD_VENDOR
3. devicetree.cb - Enable root bridge and serial port
   1. The first line must be "chip soc/Intel/<soc family>"; this path is used by the generated static.c to include the chip.h header file
4. romstage.c
   1. Add routine mainboard_romstage_entry which calls romstage_common
5. Configure coreboot build:
   1. Set LOCALVERSION
   2. FLASHMAP_OFFSET = 0x00700000
   3. Select vendor for the board
   4. Select the board
   5. CBFS_SIZE = 0x00100000
   6. Set the CPU_MICROCODE_CBFS_LEN
   7. Set the CPU_MICROCODE_CBFS_LOC
   8. Set the FSP_IMAGE_ID_STRING
   9. Set the FSP_LOC
   10. Disable GOP_SUPPORT
   11. No payload
   12. Choose the default value for all other options

Enable Serial Output

Use the following steps to enable serial output:

1. Implement the car_mainboard_pre_console_init routine in the com_init.c file:
   1. Power on and enable the UART controller
   2. Connect the UART receive and transmit data lines to the appropriate SoC pins
2. Add Makefile.inc
   1. Add com_init.c to romstage

Memory Timing Data

Memory timing data is located in the flash. This data is in the format of serial presence detect (SPD) data. Use the following steps to load the SPD data:

1. Edit Kconfig to add the DISPLAY_SPD_DATA" value which enables the display of the SPD data being passed to MemoryInit
2. Create an "spd" subdirectory
3. Create an spd/spd.c file for the SPD implementation
   1. Implement the mainboard_fill_spd_data routine
      1. Read the SPD data either from the spd.bin file or using I2C or SMBUS
      2. Fill in the pei_data structure with SPD data for each of the DIMMs
      3. Set the DIMM channel configuration
4. Add an .spd.hex file containing the memory timing data to the spd subdirectory
5. Create spd/Makefile.inc
   1. Add spd.c to romstage
   2. Add the .spd.hex file to SPD_SOURCES
6. Edit Makefile.inc to add the spd subdirectory
7. Edit romstage.c
   1. Call mainboard_fill_spd_data
   2. Add mainboard_memory_init_params to copy the SPD and DRAM configuration data from the pei_data structure into the UPDs for MemoryInit
8. Edit devicetree.cb
   1. Include the UPD parameters for MemoryInit except for:
      • Address of SPD data
      • DRAM configuration set above
9. A working FSP MemoryInit routine is required to complete debugging
10. Debug the result until port 0x80 outputs
    1. 0x34: - Just after entering raminit
    2. 0x36: - Just before displaying the UPD parameters for FSP MemoryInit
    3. 0x92: POST_FSP_MEMORY_INIT - Just before calling FSP MemoryInit
    4. 0x37: - Just after returning from FSP MemoryInit
11. Continue debugging with CONFIG_DISPLAY_HOBS enabled until TempRamExit is called

Disable PCI Devices

Ramstage's BS_DEV_ENUMERATE state displays the PCI vendor and device IDs for all of the devices in the system. Edit the devicetree.cb file:

1. Edit the devicetree.cb file:
   1. Add an entry for a PCI device.function and turn it off. The entry should look similar to:

      device pci 14.0 off end

   2. Turn on the devices for:
      • Memory Controller
      • Debug serial device
2. Debug until the BS_DEV_ENUMERATE state shows the proper state for all of the devices

Modified: 15 February 2016