From 6dc9d0352e9c2dafb46c8c827d07cfdba2d744dd Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sun, 16 Feb 2020 16:22:52 +0100 Subject: treewide: capitalize 'BIOS' Also replace 'BIOS' by coreboot when the image is 'coreboot.rom'. Change-Id: I8303b7baa9671f19a036a59775026ffd63c85273 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/38932 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- util/inteltool/inteltool.8 | 2 +- util/inteltool/spi.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'util') diff --git a/util/inteltool/inteltool.8 b/util/inteltool/inteltool.8 index 86a76bdc9a..01e3cfd7f2 100644 --- a/util/inteltool/inteltool.8 +++ b/util/inteltool/inteltool.8 @@ -32,7 +32,7 @@ Show only GPIO register differences from hardware defaults. Dump I/O Controller Hub (ICH) southbridge RCBA registers. .TP .B "\-s, \-\-spi" -Dump I/O Controller Hub (ICH) southbridge SPI registers and bios control. +Dump I/O Controller Hub (ICH) southbridge SPI registers and BIOS control. .TP .B "\-f, \-\-gfx" .RB "Dump graphics registers. " \ diff --git a/util/inteltool/spi.c b/util/inteltool/spi.c index 22ba3d42f2..e8289acaf3 100644 --- a/util/inteltool/spi.c +++ b/util/inteltool/spi.c @@ -22,7 +22,7 @@ static const io_register_t pch_bios_cntl_registers[] = { { 0x1, 1, "BLE - lock enable" }, { 0x2, 2, "SPI Read configuration" }, { 0x4, 1, "TopSwapStatus" }, - { 0x5, 1, "SMM Bios Write Protect Disable" }, + { 0x5, 1, "SMM BIOS Write Protect Disable" }, { 0x6, 2, "reserved" }, }; -- cgit v1.2.3