From 0867062412dd4bfe5a556e5f3fd85ba5b682d79b Mon Sep 17 00:00:00 2001 From: Stefan Reinauer Date: Tue, 30 Jun 2009 15:17:49 +0000 Subject: This patch unifies the use of config options in v2 to all start with CONFIG_ It's basically done with the following script and some manual fixup: VARS=`grep ^define src/config/Options.lb | cut -f2 -d\ | grep -v ^CONFIG | grep -v ^COREBOOT |grep -v ^CC` for VAR in $VARS; do find . -name .svn -prune -o -type f -exec perl -pi -e "s/(^|[^0-9a-zA-Z_]+)$VAR($|[^0-9a-zA-Z_]+)/\1CONFIG_$VAR\2/g" {} \; done Signed-off-by: Stefan Reinauer Acked-by: Ronald G. Minnich git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4381 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- util/abuild/abuild | 18 ++++++------ util/analysis/Makefile | 2 +- util/cbfstool/Makefile | 6 ++-- util/cbfstool/tools/Makefile | 2 +- util/newconfig/config.g | 24 ++++++++-------- util/options/build_opt_tbl.c | 10 +++---- util/romcc/tests/hello_world.c | 40 +++++++++++++-------------- util/romcc/tests/hello_world1.c | 40 +++++++++++++-------------- util/romcc/tests/hello_world2.c | 40 +++++++++++++-------------- util/romcc/tests/raminit_test.c | 36 ++++++++++++------------ util/romcc/tests/raminit_test1.c | 36 ++++++++++++------------ util/romcc/tests/raminit_test2.c | 36 ++++++++++++------------ util/romcc/tests/simple_test.c | 24 ++++++++-------- util/romcc/tests/simple_test1.c | 24 ++++++++-------- util/romcc/tests/simple_test20.c | 36 ++++++++++++------------ util/romcc/tests/simple_test27.c | 40 +++++++++++++-------------- util/romcc/tests/simple_test4.c | 36 ++++++++++++------------ util/vgabios/helper_mem.c | 4 +-- util/vgabios/x86emu/include/x86emu.h | 2 +- util/vgabios/x86emu/include/x86emu/fpu_regs.h | 2 +- util/vgabios/x86emu/include/x86emu/regs.h | 2 +- util/vgabios/x86emu/src/x86emu/debug.c | 6 ++-- util/vgabios/x86emu/src/x86emu/decode.c | 26 ++++++++--------- util/vgabios/x86emu/src/x86emu/fpu.c | 34 +++++++++++------------ util/vgabios/x86emu/src/x86emu/makefile | 4 +-- util/vgabios/x86emu/src/x86emu/ops.c | 28 +++++++++---------- util/vgabios/x86emu/src/x86emu/x86emu/debug.h | 16 +++++------ 27 files changed, 287 insertions(+), 287 deletions(-) (limited to 'util') diff --git a/util/abuild/abuild b/util/abuild/abuild index 47decf61eb..7dc7cf10d0 100755 --- a/util/abuild/abuild +++ b/util/abuild/abuild @@ -165,8 +165,8 @@ target VENDOR_MAINBOARD mainboard VENDOR/MAINBOARD option CC="CROSSCC" -option CROSS_COMPILE="CROSS_PREFIX" -option HOSTCC="CROSS_HOSTCC" +option CONFIG_CROSS_COMPILE="CROSS_PREFIX" +option CONFIG_HOSTCC="CROSS_HOSTCC" __COMPRESSION__ __LOGLEVEL__ @@ -175,25 +175,25 @@ EOF if [ "$TARCH" == i386 ] ; then cat <> - rule arch<>: ARCH ID {{ if (C): setarch(ID) }} + rule arch<>: CONFIG_ARCH ID {{ if (C): setarch(ID) }} partend<> rule mainboardinit<>: @@ -1969,7 +1969,7 @@ parser Config: rule payload<>: PAYLOAD DIRPATH {{ if (C): payload(DIRPATH) }} rule mainboard: - MAINBOARD PATH {{ mainboardsetup(PATH) }} + CONFIG_MAINBOARD PATH {{ mainboardsetup(PATH) }} rule romif<>: IF ID {{ c = lookup(ID) }} (romstmt<>)* @@ -2287,7 +2287,7 @@ def writemakefile(path): file.write(" %s/coreboot.rom " % j) file.write("\n") - romsize = getoption("ROM_SIZE", image) + romsize = getoption("CONFIG_ROM_SIZE", image) file.write("\n\trm -f %s\n" %(i.name)) diff --git a/util/options/build_opt_tbl.c b/util/options/build_opt_tbl.c index 075387d1d8..f4aa8af7ec 100644 --- a/util/options/build_opt_tbl.c +++ b/util/options/build_opt_tbl.c @@ -459,17 +459,17 @@ int main(int argc, char **argv) exit(1); } /* And since we are not ready to be fully general purpose yet.. */ - if ((cs->range_start/8) != LB_CKS_RANGE_START) { + if ((cs->range_start/8) != CONFIG_LB_CKS_RANGE_START) { fprintf(stderr, "Error - Range start(%d) does not match define(%d) in line\n%s\n", - cs->range_start/8, LB_CKS_RANGE_START, line); + cs->range_start/8, CONFIG_LB_CKS_RANGE_START, line); exit(1); } - if ((cs->range_end/8) != LB_CKS_RANGE_END) { + if ((cs->range_end/8) != CONFIG_LB_CKS_RANGE_END) { fprintf(stderr, "Error - Range end (%d) does not match define (%d) in line\n%s\n", - (cs->range_end/8), LB_CKS_RANGE_END, line); + (cs->range_end/8), CONFIG_LB_CKS_RANGE_END, line); exit(1); } - if ((cs->location/8) != LB_CKS_LOC) { + if ((cs->location/8) != CONFIG_LB_CKS_LOC) { fprintf(stderr, "Error - Location does not match define in line\n%s\n", line); exit(1); } diff --git a/util/romcc/tests/hello_world.c b/util/romcc/tests/hello_world.c index 6dd80d89b8..b5ce540dc9 100644 --- a/util/romcc/tests/hello_world.c +++ b/util/romcc/tests/hello_world.c @@ -9,31 +9,31 @@ unsigned char inb(unsigned short port) } /* Base Address */ -#ifndef TTYS0_BASE -#define TTYS0_BASE 0x3f8 +#ifndef CONFIG_TTYS0_BASE +#define CONFIG_TTYS0_BASE 0x3f8 #endif -#ifndef TTYS0_BAUD -#define TTYS0_BAUD 115200 +#ifndef CONFIG_TTYS0_BAUD +#define CONFIG_TTYS0_BAUD 115200 #endif -#if ((115200%TTYS0_BAUD) != 0) +#if ((115200%CONFIG_TTYS0_BAUD) != 0) #error Bad ttys0 baud rate #endif -#if TTYS0_BAUD == 115200 -#define TTYS0_DIV (1) +#if CONFIG_TTYS0_BAUD == 115200 +#define CONFIG_TTYS0_DIV (1) #else -#define TTYS0_DIV (115200/TTYS0_BAUD) +#define CONFIG_TTYS0_DIV (115200/CONFIG_TTYS0_BAUD) #endif /* Line Control Settings */ -#ifndef TTYS0_LCS +#ifndef CONFIG_TTYS0_LCS /* Set 8bit, 1 stop bit, no parity */ -#define TTYS0_LCS 0x3 +#define CONFIG_TTYS0_LCS 0x3 #endif -#define UART_LCS TTYS0_LCS +#define UART_LCS CONFIG_TTYS0_LCS /* Data */ #define UART_RBR 0x00 @@ -55,7 +55,7 @@ unsigned char inb(unsigned short port) int uart_can_tx_byte(void) { - return inb(TTYS0_BASE + UART_LSR) & 0x20; + return inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x20; } void uart_wait_to_tx_byte(void) @@ -66,14 +66,14 @@ void uart_wait_to_tx_byte(void) void uart_wait_until_sent(void) { - while(!(inb(TTYS0_BASE + UART_LSR) & 0x40)) + while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40)) ; } static void uart_tx_byte(unsigned char data) { uart_wait_to_tx_byte(); - outb(data, TTYS0_BASE + UART_TBR); + outb(data, CONFIG_TTYS0_BASE + UART_TBR); /* Make certain the data clears the fifos */ uart_wait_until_sent(); } @@ -82,14 +82,14 @@ static void uart_tx_byte(unsigned char data) void uart_init(void) { /* disable interrupts */ - outb(0x0, TTYS0_BASE + UART_IER); + outb(0x0, CONFIG_TTYS0_BASE + UART_IER); /* enable fifo's */ - outb(0x01, TTYS0_BASE + UART_FCR); + outb(0x01, CONFIG_TTYS0_BASE + UART_FCR); /* Set Baud Rate Divisor to 12 ==> 115200 Baud */ - outb(0x80 | UART_LCS, TTYS0_BASE + UART_LCR); - outb(TTYS0_DIV & 0xFF, TTYS0_BASE + UART_DLL); - outb((TTYS0_DIV >> 8) & 0xFF, TTYS0_BASE + UART_DLM); - outb(UART_LCS, TTYS0_BASE + UART_LCR); + outb(0x80 | UART_LCS, CONFIG_TTYS0_BASE + UART_LCR); + outb(CONFIG_TTYS0_DIV & 0xFF, CONFIG_TTYS0_BASE + UART_DLL); + outb((CONFIG_TTYS0_DIV >> 8) & 0xFF, CONFIG_TTYS0_BASE + UART_DLM); + outb(UART_LCS, CONFIG_TTYS0_BASE + UART_LCR); } diff --git a/util/romcc/tests/hello_world1.c b/util/romcc/tests/hello_world1.c index 6dd80d89b8..b5ce540dc9 100644 --- a/util/romcc/tests/hello_world1.c +++ b/util/romcc/tests/hello_world1.c @@ -9,31 +9,31 @@ unsigned char inb(unsigned short port) } /* Base Address */ -#ifndef TTYS0_BASE -#define TTYS0_BASE 0x3f8 +#ifndef CONFIG_TTYS0_BASE +#define CONFIG_TTYS0_BASE 0x3f8 #endif -#ifndef TTYS0_BAUD -#define TTYS0_BAUD 115200 +#ifndef CONFIG_TTYS0_BAUD +#define CONFIG_TTYS0_BAUD 115200 #endif -#if ((115200%TTYS0_BAUD) != 0) +#if ((115200%CONFIG_TTYS0_BAUD) != 0) #error Bad ttys0 baud rate #endif -#if TTYS0_BAUD == 115200 -#define TTYS0_DIV (1) +#if CONFIG_TTYS0_BAUD == 115200 +#define CONFIG_TTYS0_DIV (1) #else -#define TTYS0_DIV (115200/TTYS0_BAUD) +#define CONFIG_TTYS0_DIV (115200/CONFIG_TTYS0_BAUD) #endif /* Line Control Settings */ -#ifndef TTYS0_LCS +#ifndef CONFIG_TTYS0_LCS /* Set 8bit, 1 stop bit, no parity */ -#define TTYS0_LCS 0x3 +#define CONFIG_TTYS0_LCS 0x3 #endif -#define UART_LCS TTYS0_LCS +#define UART_LCS CONFIG_TTYS0_LCS /* Data */ #define UART_RBR 0x00 @@ -55,7 +55,7 @@ unsigned char inb(unsigned short port) int uart_can_tx_byte(void) { - return inb(TTYS0_BASE + UART_LSR) & 0x20; + return inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x20; } void uart_wait_to_tx_byte(void) @@ -66,14 +66,14 @@ void uart_wait_to_tx_byte(void) void uart_wait_until_sent(void) { - while(!(inb(TTYS0_BASE + UART_LSR) & 0x40)) + while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40)) ; } static void uart_tx_byte(unsigned char data) { uart_wait_to_tx_byte(); - outb(data, TTYS0_BASE + UART_TBR); + outb(data, CONFIG_TTYS0_BASE + UART_TBR); /* Make certain the data clears the fifos */ uart_wait_until_sent(); } @@ -82,14 +82,14 @@ static void uart_tx_byte(unsigned char data) void uart_init(void) { /* disable interrupts */ - outb(0x0, TTYS0_BASE + UART_IER); + outb(0x0, CONFIG_TTYS0_BASE + UART_IER); /* enable fifo's */ - outb(0x01, TTYS0_BASE + UART_FCR); + outb(0x01, CONFIG_TTYS0_BASE + UART_FCR); /* Set Baud Rate Divisor to 12 ==> 115200 Baud */ - outb(0x80 | UART_LCS, TTYS0_BASE + UART_LCR); - outb(TTYS0_DIV & 0xFF, TTYS0_BASE + UART_DLL); - outb((TTYS0_DIV >> 8) & 0xFF, TTYS0_BASE + UART_DLM); - outb(UART_LCS, TTYS0_BASE + UART_LCR); + outb(0x80 | UART_LCS, CONFIG_TTYS0_BASE + UART_LCR); + outb(CONFIG_TTYS0_DIV & 0xFF, CONFIG_TTYS0_BASE + UART_DLL); + outb((CONFIG_TTYS0_DIV >> 8) & 0xFF, CONFIG_TTYS0_BASE + UART_DLM); + outb(UART_LCS, CONFIG_TTYS0_BASE + UART_LCR); } diff --git a/util/romcc/tests/hello_world2.c b/util/romcc/tests/hello_world2.c index 7990dcb518..18380d37e8 100644 --- a/util/romcc/tests/hello_world2.c +++ b/util/romcc/tests/hello_world2.c @@ -9,31 +9,31 @@ unsigned char inb(unsigned short port) } /* Base Address */ -#ifndef TTYS0_BASE -#define TTYS0_BASE 0x3f8 +#ifndef CONFIG_TTYS0_BASE +#define CONFIG_TTYS0_BASE 0x3f8 #endif -#ifndef TTYS0_BAUD -#define TTYS0_BAUD 115200 +#ifndef CONFIG_TTYS0_BAUD +#define CONFIG_TTYS0_BAUD 115200 #endif -#if ((115200%TTYS0_BAUD) != 0) +#if ((115200%CONFIG_TTYS0_BAUD) != 0) #error Bad ttys0 baud rate #endif -#if TTYS0_BAUD == 115200 -#define TTYS0_DIV (1) +#if CONFIG_TTYS0_BAUD == 115200 +#define CONFIG_TTYS0_DIV (1) #else -#define TTYS0_DIV (115200/TTYS0_BAUD) +#define CONFIG_TTYS0_DIV (115200/CONFIG_TTYS0_BAUD) #endif /* Line Control Settings */ -#ifndef TTYS0_LCS +#ifndef CONFIG_TTYS0_LCS /* Set 8bit, 1 stop bit, no parity */ -#define TTYS0_LCS 0x3 +#define CONFIG_TTYS0_LCS 0x3 #endif -#define UART_LCS TTYS0_LCS +#define UART_LCS CONFIG_TTYS0_LCS /* Data */ #define UART_RBR 0x00 @@ -55,7 +55,7 @@ unsigned char inb(unsigned short port) int uart_can_tx_byte(void) { - return inb(TTYS0_BASE + UART_LSR) & 0x20; + return inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x20; } void uart_wait_to_tx_byte(void) @@ -66,14 +66,14 @@ void uart_wait_to_tx_byte(void) void uart_wait_until_sent(void) { - while(!(inb(TTYS0_BASE + UART_LSR) & 0x40)) + while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40)) ; } static void uart_tx_byte(unsigned char data) { uart_wait_to_tx_byte(); - outb(data, TTYS0_BASE + UART_TBR); + outb(data, CONFIG_TTYS0_BASE + UART_TBR); /* Make certain the data clears the fifos */ uart_wait_until_sent(); } @@ -82,14 +82,14 @@ static void uart_tx_byte(unsigned char data) void uart_init(void) { /* disable interrupts */ - outb(0x0, TTYS0_BASE + UART_IER); + outb(0x0, CONFIG_TTYS0_BASE + UART_IER); /* enable fifo's */ - outb(0x01, TTYS0_BASE + UART_FCR); + outb(0x01, CONFIG_TTYS0_BASE + UART_FCR); /* Set Baud Rate Divisor to 12 ==> 115200 Baud */ - outb(0x80 | UART_LCS, TTYS0_BASE + UART_LCR); - outb(TTYS0_DIV & 0xFF, TTYS0_BASE + UART_DLL); - outb((TTYS0_DIV >> 8) & 0xFF, TTYS0_BASE + UART_DLM); - outb(UART_LCS, TTYS0_BASE + UART_LCR); + outb(0x80 | UART_LCS, CONFIG_TTYS0_BASE + UART_LCR); + outb(CONFIG_TTYS0_DIV & 0xFF, CONFIG_TTYS0_BASE + UART_DLL); + outb((CONFIG_TTYS0_DIV >> 8) & 0xFF, CONFIG_TTYS0_BASE + UART_DLM); + outb(UART_LCS, CONFIG_TTYS0_BASE + UART_LCR); } diff --git a/util/romcc/tests/raminit_test.c b/util/romcc/tests/raminit_test.c index 9b6cf5d31c..2c6fa8c750 100644 --- a/util/romcc/tests/raminit_test.c +++ b/util/romcc/tests/raminit_test.c @@ -83,27 +83,27 @@ static void pcibios_write_config_dword( } /* Base Address */ -#ifndef TTYS0_BASE -#define TTYS0_BASE 0x3f8 +#ifndef CONFIG_TTYS0_BASE +#define CONFIG_TTYS0_BASE 0x3f8 #endif -#ifndef TTYS0_BAUD -#define TTYS0_BAUD 115200 +#ifndef CONFIG_TTYS0_BAUD +#define CONFIG_TTYS0_BAUD 115200 #endif -#if ((115200%TTYS0_BAUD) != 0) +#if ((115200%CONFIG_TTYS0_BAUD) != 0) #error Bad ttys0 baud rate #endif -#define TTYS0_DIV (115200/TTYS0_BAUD) +#define CONFIG_TTYS0_DIV (115200/CONFIG_TTYS0_BAUD) /* Line Control Settings */ -#ifndef TTYS0_LCS +#ifndef CONFIG_TTYS0_LCS /* Set 8bit, 1 stop bit, no parity */ -#define TTYS0_LCS 0x3 +#define CONFIG_TTYS0_LCS 0x3 #endif -#define UART_LCS TTYS0_LCS +#define UART_LCS CONFIG_TTYS0_LCS /* Data */ #define UART_RBR 0x00 @@ -125,7 +125,7 @@ static void pcibios_write_config_dword( int uart_can_tx_byte(void) { - return inb(TTYS0_BASE + UART_LSR) & 0x20; + return inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x20; } void uart_wait_to_tx_byte(void) @@ -136,14 +136,14 @@ void uart_wait_to_tx_byte(void) void uart_wait_until_sent(void) { - while(!(inb(TTYS0_BASE + UART_LSR) & 0x40)) + while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40)) ; } void uart_tx_byte(unsigned char data) { uart_wait_to_tx_byte(); - outb(data, TTYS0_BASE + UART_TBR); + outb(data, CONFIG_TTYS0_BASE + UART_TBR); /* Make certain the data clears the fifos */ uart_wait_until_sent(); } @@ -151,14 +151,14 @@ void uart_tx_byte(unsigned char data) void uart_init(void) { /* disable interrupts */ - outb(0x0, TTYS0_BASE + UART_IER); + outb(0x0, CONFIG_TTYS0_BASE + UART_IER); /* enable fifo's */ - outb(0x01, TTYS0_BASE + UART_FCR); + outb(0x01, CONFIG_TTYS0_BASE + UART_FCR); /* Set Baud Rate Divisor to 12 ==> 115200 Baud */ - outb(0x80 | UART_LCS, TTYS0_BASE + UART_LCR); - outb(TTYS0_DIV & 0xFF, TTYS0_BASE + UART_DLL); - outb((TTYS0_DIV >> 8) & 0xFF, TTYS0_BASE + UART_DLM); - outb(UART_LCS, TTYS0_BASE + UART_LCR); + outb(0x80 | UART_LCS, CONFIG_TTYS0_BASE + UART_LCR); + outb(CONFIG_TTYS0_DIV & 0xFF, CONFIG_TTYS0_BASE + UART_DLL); + outb((CONFIG_TTYS0_DIV >> 8) & 0xFF, CONFIG_TTYS0_BASE + UART_DLM); + outb(UART_LCS, CONFIG_TTYS0_BASE + UART_LCR); } void __console_tx_char(unsigned char byte) diff --git a/util/romcc/tests/raminit_test1.c b/util/romcc/tests/raminit_test1.c index 9b6cf5d31c..2c6fa8c750 100644 --- a/util/romcc/tests/raminit_test1.c +++ b/util/romcc/tests/raminit_test1.c @@ -83,27 +83,27 @@ static void pcibios_write_config_dword( } /* Base Address */ -#ifndef TTYS0_BASE -#define TTYS0_BASE 0x3f8 +#ifndef CONFIG_TTYS0_BASE +#define CONFIG_TTYS0_BASE 0x3f8 #endif -#ifndef TTYS0_BAUD -#define TTYS0_BAUD 115200 +#ifndef CONFIG_TTYS0_BAUD +#define CONFIG_TTYS0_BAUD 115200 #endif -#if ((115200%TTYS0_BAUD) != 0) +#if ((115200%CONFIG_TTYS0_BAUD) != 0) #error Bad ttys0 baud rate #endif -#define TTYS0_DIV (115200/TTYS0_BAUD) +#define CONFIG_TTYS0_DIV (115200/CONFIG_TTYS0_BAUD) /* Line Control Settings */ -#ifndef TTYS0_LCS +#ifndef CONFIG_TTYS0_LCS /* Set 8bit, 1 stop bit, no parity */ -#define TTYS0_LCS 0x3 +#define CONFIG_TTYS0_LCS 0x3 #endif -#define UART_LCS TTYS0_LCS +#define UART_LCS CONFIG_TTYS0_LCS /* Data */ #define UART_RBR 0x00 @@ -125,7 +125,7 @@ static void pcibios_write_config_dword( int uart_can_tx_byte(void) { - return inb(TTYS0_BASE + UART_LSR) & 0x20; + return inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x20; } void uart_wait_to_tx_byte(void) @@ -136,14 +136,14 @@ void uart_wait_to_tx_byte(void) void uart_wait_until_sent(void) { - while(!(inb(TTYS0_BASE + UART_LSR) & 0x40)) + while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40)) ; } void uart_tx_byte(unsigned char data) { uart_wait_to_tx_byte(); - outb(data, TTYS0_BASE + UART_TBR); + outb(data, CONFIG_TTYS0_BASE + UART_TBR); /* Make certain the data clears the fifos */ uart_wait_until_sent(); } @@ -151,14 +151,14 @@ void uart_tx_byte(unsigned char data) void uart_init(void) { /* disable interrupts */ - outb(0x0, TTYS0_BASE + UART_IER); + outb(0x0, CONFIG_TTYS0_BASE + UART_IER); /* enable fifo's */ - outb(0x01, TTYS0_BASE + UART_FCR); + outb(0x01, CONFIG_TTYS0_BASE + UART_FCR); /* Set Baud Rate Divisor to 12 ==> 115200 Baud */ - outb(0x80 | UART_LCS, TTYS0_BASE + UART_LCR); - outb(TTYS0_DIV & 0xFF, TTYS0_BASE + UART_DLL); - outb((TTYS0_DIV >> 8) & 0xFF, TTYS0_BASE + UART_DLM); - outb(UART_LCS, TTYS0_BASE + UART_LCR); + outb(0x80 | UART_LCS, CONFIG_TTYS0_BASE + UART_LCR); + outb(CONFIG_TTYS0_DIV & 0xFF, CONFIG_TTYS0_BASE + UART_DLL); + outb((CONFIG_TTYS0_DIV >> 8) & 0xFF, CONFIG_TTYS0_BASE + UART_DLM); + outb(UART_LCS, CONFIG_TTYS0_BASE + UART_LCR); } void __console_tx_char(unsigned char byte) diff --git a/util/romcc/tests/raminit_test2.c b/util/romcc/tests/raminit_test2.c index 68747a7a91..2294b34e78 100644 --- a/util/romcc/tests/raminit_test2.c +++ b/util/romcc/tests/raminit_test2.c @@ -83,27 +83,27 @@ static void pcibios_write_config_dword( } /* Base Address */ -#ifndef TTYS0_BASE -#define TTYS0_BASE 0x3f8 +#ifndef CONFIG_TTYS0_BASE +#define CONFIG_TTYS0_BASE 0x3f8 #endif -#ifndef TTYS0_BAUD -#define TTYS0_BAUD 115200 +#ifndef CONFIG_TTYS0_BAUD +#define CONFIG_TTYS0_BAUD 115200 #endif -#if ((115200%TTYS0_BAUD) != 0) +#if ((115200%CONFIG_TTYS0_BAUD) != 0) #error Bad ttys0 baud rate #endif -#define TTYS0_DIV (115200/TTYS0_BAUD) +#define CONFIG_TTYS0_DIV (115200/CONFIG_TTYS0_BAUD) /* Line Control Settings */ -#ifndef TTYS0_LCS +#ifndef CONFIG_TTYS0_LCS /* Set 8bit, 1 stop bit, no parity */ -#define TTYS0_LCS 0x3 +#define CONFIG_TTYS0_LCS 0x3 #endif -#define UART_LCS TTYS0_LCS +#define UART_LCS CONFIG_TTYS0_LCS /* Data */ #define UART_RBR 0x00 @@ -125,7 +125,7 @@ static void pcibios_write_config_dword( int uart_can_tx_byte(void) { - return inb(TTYS0_BASE + UART_LSR) & 0x20; + return inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x20; } void uart_wait_to_tx_byte(void) @@ -136,14 +136,14 @@ void uart_wait_to_tx_byte(void) void uart_wait_until_sent(void) { - while(!(inb(TTYS0_BASE + UART_LSR) & 0x40)) + while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40)) ; } void uart_tx_byte(unsigned char data) { uart_wait_to_tx_byte(); - outb(data, TTYS0_BASE + UART_TBR); + outb(data, CONFIG_TTYS0_BASE + UART_TBR); /* Make certain the data clears the fifos */ uart_wait_until_sent(); } @@ -151,14 +151,14 @@ void uart_tx_byte(unsigned char data) void uart_init(void) { /* disable interrupts */ - outb(0x0, TTYS0_BASE + UART_IER); + outb(0x0, CONFIG_TTYS0_BASE + UART_IER); /* enable fifo's */ - outb(0x01, TTYS0_BASE + UART_FCR); + outb(0x01, CONFIG_TTYS0_BASE + UART_FCR); /* Set Baud Rate Divisor to 12 ==> 115200 Baud */ - outb(0x80 | UART_LCS, TTYS0_BASE + UART_LCR); - outb(TTYS0_DIV & 0xFF, TTYS0_BASE + UART_DLL); - outb((TTYS0_DIV >> 8) & 0xFF, TTYS0_BASE + UART_DLM); - outb(UART_LCS, TTYS0_BASE + UART_LCR); + outb(0x80 | UART_LCS, CONFIG_TTYS0_BASE + UART_LCR); + outb(CONFIG_TTYS0_DIV & 0xFF, CONFIG_TTYS0_BASE + UART_DLL); + outb((CONFIG_TTYS0_DIV >> 8) & 0xFF, CONFIG_TTYS0_BASE + UART_DLM); + outb(UART_LCS, CONFIG_TTYS0_BASE + UART_LCR); } void __console_tx_char(unsigned char byte) diff --git a/util/romcc/tests/simple_test.c b/util/romcc/tests/simple_test.c index feacbfdc38..4065c51a2f 100644 --- a/util/romcc/tests/simple_test.c +++ b/util/romcc/tests/simple_test.c @@ -25,27 +25,27 @@ static unsigned int config_cmd2(unsigned char bus, unsigned devfn, unsigned wher } /* Base Address */ -#ifndef TTYS0_BASE -#define TTYS0_BASE 0x3f8 +#ifndef CONFIG_TTYS0_BASE +#define CONFIG_TTYS0_BASE 0x3f8 #endif -#ifndef TTYS0_BAUD -#define TTYS0_BAUD 115200 +#ifndef CONFIG_TTYS0_BAUD +#define CONFIG_TTYS0_BAUD 115200 #endif -#if ((115200%TTYS0_BAUD) != 0) +#if ((115200%CONFIG_TTYS0_BAUD) != 0) #error Bad ttys0 baud rate #endif -#define TTYS0_DIV (115200/TTYS0_BAUD) +#define CONFIG_TTYS0_DIV (115200/CONFIG_TTYS0_BAUD) /* Line Control Settings */ -#ifndef TTYS0_LCS +#ifndef CONFIG_TTYS0_LCS /* Set 8bit, 1 stop bit, no parity */ -#define TTYS0_LCS 0x3 +#define CONFIG_TTYS0_LCS 0x3 #endif -#define UART_LCS TTYS0_LCS +#define UART_LCS CONFIG_TTYS0_LCS /* Data */ #define UART_RBR 0x00 @@ -67,7 +67,7 @@ static unsigned int config_cmd2(unsigned char bus, unsigned devfn, unsigned wher int uart_can_tx_byte(void) { - return inb(TTYS0_BASE + UART_LSR) & 0x20; + return inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x20; } void uart_wait_to_tx_byte(void) @@ -78,14 +78,14 @@ void uart_wait_to_tx_byte(void) void uart_wait_until_sent(void) { - while(!(inb(TTYS0_BASE + UART_LSR) & 0x40)) + while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40)) ; } void uart_tx_byte(unsigned char data) { uart_wait_to_tx_byte(); - outb(data, TTYS0_BASE + UART_TBR); + outb(data, CONFIG_TTYS0_BASE + UART_TBR); /* Make certain the data clears the fifos */ uart_wait_until_sent(); } diff --git a/util/romcc/tests/simple_test1.c b/util/romcc/tests/simple_test1.c index feacbfdc38..4065c51a2f 100644 --- a/util/romcc/tests/simple_test1.c +++ b/util/romcc/tests/simple_test1.c @@ -25,27 +25,27 @@ static unsigned int config_cmd2(unsigned char bus, unsigned devfn, unsigned wher } /* Base Address */ -#ifndef TTYS0_BASE -#define TTYS0_BASE 0x3f8 +#ifndef CONFIG_TTYS0_BASE +#define CONFIG_TTYS0_BASE 0x3f8 #endif -#ifndef TTYS0_BAUD -#define TTYS0_BAUD 115200 +#ifndef CONFIG_TTYS0_BAUD +#define CONFIG_TTYS0_BAUD 115200 #endif -#if ((115200%TTYS0_BAUD) != 0) +#if ((115200%CONFIG_TTYS0_BAUD) != 0) #error Bad ttys0 baud rate #endif -#define TTYS0_DIV (115200/TTYS0_BAUD) +#define CONFIG_TTYS0_DIV (115200/CONFIG_TTYS0_BAUD) /* Line Control Settings */ -#ifndef TTYS0_LCS +#ifndef CONFIG_TTYS0_LCS /* Set 8bit, 1 stop bit, no parity */ -#define TTYS0_LCS 0x3 +#define CONFIG_TTYS0_LCS 0x3 #endif -#define UART_LCS TTYS0_LCS +#define UART_LCS CONFIG_TTYS0_LCS /* Data */ #define UART_RBR 0x00 @@ -67,7 +67,7 @@ static unsigned int config_cmd2(unsigned char bus, unsigned devfn, unsigned wher int uart_can_tx_byte(void) { - return inb(TTYS0_BASE + UART_LSR) & 0x20; + return inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x20; } void uart_wait_to_tx_byte(void) @@ -78,14 +78,14 @@ void uart_wait_to_tx_byte(void) void uart_wait_until_sent(void) { - while(!(inb(TTYS0_BASE + UART_LSR) & 0x40)) + while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40)) ; } void uart_tx_byte(unsigned char data) { uart_wait_to_tx_byte(); - outb(data, TTYS0_BASE + UART_TBR); + outb(data, CONFIG_TTYS0_BASE + UART_TBR); /* Make certain the data clears the fifos */ uart_wait_until_sent(); } diff --git a/util/romcc/tests/simple_test20.c b/util/romcc/tests/simple_test20.c index 71af19cf2f..1998853af1 100644 --- a/util/romcc/tests/simple_test20.c +++ b/util/romcc/tests/simple_test20.c @@ -33,27 +33,27 @@ static unsigned int pcibios_read_config_dword( /* Base Address */ -#ifndef TTYS0_BASE -#define TTYS0_BASE 0x3f8 +#ifndef CONFIG_TTYS0_BASE +#define CONFIG_TTYS0_BASE 0x3f8 #endif -#ifndef TTYS0_BAUD -#define TTYS0_BAUD 115200 +#ifndef CONFIG_TTYS0_BAUD +#define CONFIG_TTYS0_BAUD 115200 #endif -#if ((115200%TTYS0_BAUD) != 0) +#if ((115200%CONFIG_TTYS0_BAUD) != 0) #error Bad ttys0 baud rate #endif -#define TTYS0_DIV (115200/TTYS0_BAUD) +#define CONFIG_TTYS0_DIV (115200/CONFIG_TTYS0_BAUD) /* Line Control Settings */ -#ifndef TTYS0_LCS +#ifndef CONFIG_TTYS0_LCS /* Set 8bit, 1 stop bit, no parity */ -#define TTYS0_LCS 0x3 +#define CONFIG_TTYS0_LCS 0x3 #endif -#define UART_LCS TTYS0_LCS +#define UART_LCS CONFIG_TTYS0_LCS /* Data */ #define UART_RBR 0x00 @@ -75,7 +75,7 @@ static unsigned int pcibios_read_config_dword( int uart_can_tx_byte(void) { - return inb(TTYS0_BASE + UART_LSR) & 0x20; + return inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x20; } void uart_wait_to_tx_byte(void) @@ -86,14 +86,14 @@ void uart_wait_to_tx_byte(void) void uart_wait_until_sent(void) { - while(!(inb(TTYS0_BASE + UART_LSR) & 0x40)) + while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40)) ; } void uart_tx_byte(unsigned char data) { uart_wait_to_tx_byte(); - outb(data, TTYS0_BASE + UART_TBR); + outb(data, CONFIG_TTYS0_BASE + UART_TBR); /* Make certain the data clears the fifos */ uart_wait_until_sent(); } @@ -101,14 +101,14 @@ void uart_tx_byte(unsigned char data) void uart_init(void) { /* disable interrupts */ - outb(0x0, TTYS0_BASE + UART_IER); + outb(0x0, CONFIG_TTYS0_BASE + UART_IER); /* enable fifo's */ - outb(0x01, TTYS0_BASE + UART_FCR); + outb(0x01, CONFIG_TTYS0_BASE + UART_FCR); /* Set Baud Rate Divisor to 12 ==> 115200 Baud */ - outb(0x80 | UART_LCS, TTYS0_BASE + UART_LCR); - outb(TTYS0_DIV & 0xFF, TTYS0_BASE + UART_DLL); - outb((TTYS0_DIV >> 8) & 0xFF, TTYS0_BASE + UART_DLM); - outb(UART_LCS, TTYS0_BASE + UART_LCR); + outb(0x80 | UART_LCS, CONFIG_TTYS0_BASE + UART_LCR); + outb(CONFIG_TTYS0_DIV & 0xFF, CONFIG_TTYS0_BASE + UART_DLL); + outb((CONFIG_TTYS0_DIV >> 8) & 0xFF, CONFIG_TTYS0_BASE + UART_DLM); + outb(UART_LCS, CONFIG_TTYS0_BASE + UART_LCR); } void __console_tx_char(unsigned char byte) diff --git a/util/romcc/tests/simple_test27.c b/util/romcc/tests/simple_test27.c index d40e43f1c4..f278f62e8a 100644 --- a/util/romcc/tests/simple_test27.c +++ b/util/romcc/tests/simple_test27.c @@ -9,31 +9,31 @@ unsigned char inb(unsigned short port) } /* Base Address */ -#ifndef TTYS0_BASE -#define TTYS0_BASE 0x3f8 +#ifndef CONFIG_TTYS0_BASE +#define CONFIG_TTYS0_BASE 0x3f8 #endif -#ifndef TTYS0_BAUD -#define TTYS0_BAUD 115200 +#ifndef CONFIG_TTYS0_BAUD +#define CONFIG_TTYS0_BAUD 115200 #endif -#if ((115200%TTYS0_BAUD) != 0) +#if ((115200%CONFIG_TTYS0_BAUD) != 0) #error Bad ttys0 baud rate #endif -#if TTYS0_BAUD == 115200 -#define TTYS0_DIV (1) +#if CONFIG_TTYS0_BAUD == 115200 +#define CONFIG_TTYS0_DIV (1) #else -#define TTYS0_DIV (115200/TTYS0_BAUD) +#define CONFIG_TTYS0_DIV (115200/CONFIG_TTYS0_BAUD) #endif /* Line Control Settings */ -#ifndef TTYS0_LCS +#ifndef CONFIG_TTYS0_LCS /* Set 8bit, 1 stop bit, no parity */ -#define TTYS0_LCS 0x3 +#define CONFIG_TTYS0_LCS 0x3 #endif -#define UART_LCS TTYS0_LCS +#define UART_LCS CONFIG_TTYS0_LCS /* Data */ #define UART_RBR 0x00 @@ -55,7 +55,7 @@ unsigned char inb(unsigned short port) int uart_can_tx_byte(void) { - return inb(TTYS0_BASE + UART_LSR) & 0x20; + return inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x20; } void uart_wait_to_tx_byte(void) @@ -66,14 +66,14 @@ void uart_wait_to_tx_byte(void) void uart_wait_until_sent(void) { - while(!(inb(TTYS0_BASE + UART_LSR) & 0x40)) + while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40)) ; } static void uart_tx_byte(unsigned char data) { uart_wait_to_tx_byte(); - outb(data, TTYS0_BASE + UART_TBR); + outb(data, CONFIG_TTYS0_BASE + UART_TBR); /* Make certain the data clears the fifos */ uart_wait_until_sent(); } @@ -82,14 +82,14 @@ static void uart_tx_byte(unsigned char data) void uart_init(void) { /* disable interrupts */ - outb(0x0, TTYS0_BASE + UART_IER); + outb(0x0, CONFIG_TTYS0_BASE + UART_IER); /* enable fifo's */ - outb(0x01, TTYS0_BASE + UART_FCR); + outb(0x01, CONFIG_TTYS0_BASE + UART_FCR); /* Set Baud Rate Divisor to 12 ==> 115200 Baud */ - outb(0x80 | UART_LCS, TTYS0_BASE + UART_LCR); - outb(TTYS0_DIV & 0xFF, TTYS0_BASE + UART_DLL); - outb((TTYS0_DIV >> 8) & 0xFF, TTYS0_BASE + UART_DLM); - outb(UART_LCS, TTYS0_BASE + UART_LCR); + outb(0x80 | UART_LCS, CONFIG_TTYS0_BASE + UART_LCR); + outb(CONFIG_TTYS0_DIV & 0xFF, CONFIG_TTYS0_BASE + UART_DLL); + outb((CONFIG_TTYS0_DIV >> 8) & 0xFF, CONFIG_TTYS0_BASE + UART_DLM); + outb(UART_LCS, CONFIG_TTYS0_BASE + UART_LCR); } diff --git a/util/romcc/tests/simple_test4.c b/util/romcc/tests/simple_test4.c index 57af2af390..4f72dcad67 100644 --- a/util/romcc/tests/simple_test4.c +++ b/util/romcc/tests/simple_test4.c @@ -96,27 +96,27 @@ int log2(int value) /* Base Address */ -#ifndef TTYS0_BASE -#define TTYS0_BASE 0x3f8 +#ifndef CONFIG_TTYS0_BASE +#define CONFIG_TTYS0_BASE 0x3f8 #endif -#ifndef TTYS0_BAUD -#define TTYS0_BAUD 115200 +#ifndef CONFIG_TTYS0_BAUD +#define CONFIG_TTYS0_BAUD 115200 #endif -#if ((115200%TTYS0_BAUD) != 0) +#if ((115200%CONFIG_TTYS0_BAUD) != 0) #error Bad ttys0 baud rate #endif -#define TTYS0_DIV (115200/TTYS0_BAUD) +#define CONFIG_TTYS0_DIV (115200/CONFIG_TTYS0_BAUD) /* Line Control Settings */ -#ifndef TTYS0_LCS +#ifndef CONFIG_TTYS0_LCS /* Set 8bit, 1 stop bit, no parity */ -#define TTYS0_LCS 0x3 +#define CONFIG_TTYS0_LCS 0x3 #endif -#define UART_LCS TTYS0_LCS +#define UART_LCS CONFIG_TTYS0_LCS /* Data */ #define UART_RBR 0x00 @@ -138,7 +138,7 @@ int log2(int value) int uart_can_tx_byte(void) { - return inb(TTYS0_BASE + UART_LSR) & 0x20; + return inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x20; } void uart_wait_to_tx_byte(void) @@ -149,14 +149,14 @@ void uart_wait_to_tx_byte(void) void uart_wait_until_sent(void) { - while(!(inb(TTYS0_BASE + UART_LSR) & 0x40)) + while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40)) ; } void uart_tx_byte(unsigned char data) { uart_wait_to_tx_byte(); - outb(data, TTYS0_BASE + UART_TBR); + outb(data, CONFIG_TTYS0_BASE + UART_TBR); /* Make certain the data clears the fifos */ uart_wait_until_sent(); } @@ -164,14 +164,14 @@ void uart_tx_byte(unsigned char data) void uart_init(void) { /* disable interrupts */ - outb(0x0, TTYS0_BASE + UART_IER); + outb(0x0, CONFIG_TTYS0_BASE + UART_IER); /* enable fifo's */ - outb(0x01, TTYS0_BASE + UART_FCR); + outb(0x01, CONFIG_TTYS0_BASE + UART_FCR); /* Set Baud Rate Divisor to 12 ==> 115200 Baud */ - outb(0x80 | UART_LCS, TTYS0_BASE + UART_LCR); - outb(TTYS0_DIV & 0xFF, TTYS0_BASE + UART_DLL); - outb((TTYS0_DIV >> 8) & 0xFF, TTYS0_BASE + UART_DLM); - outb(UART_LCS, TTYS0_BASE + UART_LCR); + outb(0x80 | UART_LCS, CONFIG_TTYS0_BASE + UART_LCR); + outb(CONFIG_TTYS0_DIV & 0xFF, CONFIG_TTYS0_BASE + UART_DLL); + outb((CONFIG_TTYS0_DIV >> 8) & 0xFF, CONFIG_TTYS0_BASE + UART_DLM); + outb(UART_LCS, CONFIG_TTYS0_BASE + UART_LCR); } void __console_tx_char(unsigned char byte) diff --git a/util/vgabios/helper_mem.c b/util/vgabios/helper_mem.c index 50a303b45e..3e201c00a8 100644 --- a/util/vgabios/helper_mem.c +++ b/util/vgabios/helper_mem.c @@ -24,7 +24,7 @@ static const OptionInfoRec INT10Options[] = { }; #endif -#ifdef DEBUG +#ifdef CONFIG_DEBUG void dprint(unsigned long start, unsigned long size) { int i, j; @@ -44,7 +44,7 @@ void dprint(unsigned long start, unsigned long size) } printf("\n"); } -#endif /* DEBUG */ +#endif /* CONFIG_DEBUG */ #if 0 #ifndef _PC diff --git a/util/vgabios/x86emu/include/x86emu.h b/util/vgabios/x86emu/include/x86emu.h index 6ddf39e24d..d1133029d4 100755 --- a/util/vgabios/x86emu/include/x86emu.h +++ b/util/vgabios/x86emu/include/x86emu.h @@ -155,7 +155,7 @@ void X86EMU_prepareForInt(int num); void X86EMU_exec(void); void X86EMU_halt_sys(void); -#ifdef DEBUG +#ifdef CONFIG_DEBUG #define HALT_SYS() \ printk("halt_sys: file %s, line %d\n", __FILE__, __LINE__), \ X86EMU_halt_sys() diff --git a/util/vgabios/x86emu/include/x86emu/fpu_regs.h b/util/vgabios/x86emu/include/x86emu/fpu_regs.h index 56e9a04d75..efc13ef2be 100755 --- a/util/vgabios/x86emu/include/x86emu/fpu_regs.h +++ b/util/vgabios/x86emu/include/x86emu/fpu_regs.h @@ -102,7 +102,7 @@ struct x86_fpu_registers { #endif /* X86_FPU_SUPPORT */ -#ifdef DEBUG +#ifdef CONFIG_DEBUG # define DECODE_PRINTINSTR32(t,mod,rh,rl) \ DECODE_PRINTF(t[(mod<<3)+(rh)]); # define DECODE_PRINTINSTR256(t,mod,rh,rl) \ diff --git a/util/vgabios/x86emu/include/x86emu/regs.h b/util/vgabios/x86emu/include/x86emu/regs.h index e77c56435b..ba6ea1ce2d 100755 --- a/util/vgabios/x86emu/include/x86emu/regs.h +++ b/util/vgabios/x86emu/include/x86emu/regs.h @@ -275,7 +275,7 @@ typedef struct { u32 mode; volatile int intr; /* mask of pending interrupts */ int debug; -#ifdef DEBUG +#ifdef CONFIG_DEBUG int check; u16 saved_ip; u16 saved_cs; diff --git a/util/vgabios/x86emu/src/x86emu/debug.c b/util/vgabios/x86emu/src/x86emu/debug.c index b69b86f8be..b39c30fa1b 100644 --- a/util/vgabios/x86emu/src/x86emu/debug.c +++ b/util/vgabios/x86emu/src/x86emu/debug.c @@ -42,7 +42,7 @@ /*----------------------------- Implementation ----------------------------*/ -#ifdef DEBUG +#ifdef CONFIG_DEBUG static void print_encoded_bytes (u16 s, u16 o); static void print_decoded_instruction (void); @@ -90,7 +90,7 @@ static void disassemble_forward (u16 seg, u16 off, int n) * flag associated with the "execution", and we are using a copy * of the register struct. All the major opcodes, once fully * decoded, have the following two steps: TRACE_REGS(r,m); - * SINGLE_STEP(r,m); which disappear if DEBUG is not defined to + * SINGLE_STEP(r,m); which disappear if CONFIG_DEBUG is not defined to * the preprocessor. The TRACE_REGS macro expands to: * * if (debug&DEBUG_DISASSEMBLE) @@ -354,7 +354,7 @@ static int parse_line (char *s, int *ps, int *n) } } -#endif /* DEBUG */ +#endif /* CONFIG_DEBUG */ void x86emu_dump_regs (void) { diff --git a/util/vgabios/x86emu/src/x86emu/decode.c b/util/vgabios/x86emu/src/x86emu/decode.c index 910d1e9796..f31768c720 100644 --- a/util/vgabios/x86emu/src/x86emu/decode.c +++ b/util/vgabios/x86emu/src/x86emu/decode.c @@ -283,7 +283,7 @@ _INLINE u32 get_data_segment(void) case SYSMODE_SEGOVR_SS | SYSMODE_SEG_DS_SS: return M.x86.R_SS; default: -#ifdef DEBUG +#ifdef CONFIG_DEBUG printk("error: should not happen: multiple overrides.\n"); #endif HALT_SYS(); @@ -303,7 +303,7 @@ NOTE: Do not inline this function as (*sys_rdX) is already inline! u8 fetch_data_byte( uint offset) { -#ifdef DEBUG +#ifdef CONFIG_DEBUG if (CHECK_DATA_ACCESS()) x86emu_check_data_access((u16)get_data_segment(), offset); #endif @@ -322,7 +322,7 @@ NOTE: Do not inline this function as (*sys_rdX) is already inline! u16 fetch_data_word( uint offset) { -#ifdef DEBUG +#ifdef CONFIG_DEBUG if (CHECK_DATA_ACCESS()) x86emu_check_data_access((u16)get_data_segment(), offset); #endif @@ -341,7 +341,7 @@ NOTE: Do not inline this function as (*sys_rdX) is already inline! u32 fetch_data_long( uint offset) { -#ifdef DEBUG +#ifdef CONFIG_DEBUG if (CHECK_DATA_ACCESS()) x86emu_check_data_access((u16)get_data_segment(), offset); #endif @@ -362,7 +362,7 @@ u8 fetch_data_byte_abs( uint segment, uint offset) { -#ifdef DEBUG +#ifdef CONFIG_DEBUG if (CHECK_DATA_ACCESS()) x86emu_check_data_access(segment, offset); #endif @@ -383,7 +383,7 @@ u16 fetch_data_word_abs( uint segment, uint offset) { -#ifdef DEBUG +#ifdef CONFIG_DEBUG if (CHECK_DATA_ACCESS()) x86emu_check_data_access(segment, offset); #endif @@ -404,7 +404,7 @@ u32 fetch_data_long_abs( uint segment, uint offset) { -#ifdef DEBUG +#ifdef CONFIG_DEBUG if (CHECK_DATA_ACCESS()) x86emu_check_data_access(segment, offset); #endif @@ -426,7 +426,7 @@ void store_data_byte( uint offset, u8 val) { -#ifdef DEBUG +#ifdef CONFIG_DEBUG if (CHECK_DATA_ACCESS()) x86emu_check_data_access((u16)get_data_segment(), offset); #endif @@ -448,7 +448,7 @@ void store_data_word( uint offset, u16 val) { -#ifdef DEBUG +#ifdef CONFIG_DEBUG if (CHECK_DATA_ACCESS()) x86emu_check_data_access((u16)get_data_segment(), offset); #endif @@ -470,7 +470,7 @@ void store_data_long( uint offset, u32 val) { -#ifdef DEBUG +#ifdef CONFIG_DEBUG if (CHECK_DATA_ACCESS()) x86emu_check_data_access((u16)get_data_segment(), offset); #endif @@ -493,7 +493,7 @@ void store_data_byte_abs( uint offset, u8 val) { -#ifdef DEBUG +#ifdef CONFIG_DEBUG if (CHECK_DATA_ACCESS()) x86emu_check_data_access(segment, offset); #endif @@ -516,7 +516,7 @@ void store_data_word_abs( uint offset, u16 val) { -#ifdef DEBUG +#ifdef CONFIG_DEBUG if (CHECK_DATA_ACCESS()) x86emu_check_data_access(segment, offset); #endif @@ -539,7 +539,7 @@ void store_data_long_abs( uint offset, u32 val) { -#ifdef DEBUG +#ifdef CONFIG_DEBUG if (CHECK_DATA_ACCESS()) x86emu_check_data_access(segment, offset); #endif diff --git a/util/vgabios/x86emu/src/x86emu/fpu.c b/util/vgabios/x86emu/src/x86emu/fpu.c index 5da363d6d5..54ca69bee6 100644 --- a/util/vgabios/x86emu/src/x86emu/fpu.c +++ b/util/vgabios/x86emu/src/x86emu/fpu.c @@ -50,7 +50,7 @@ void x86emuOp_esc_coprocess_d8(u8 X86EMU_UNUSED(op1)) END_OF_INSTR_NO_TRACE(); } -#ifdef DEBUG +#ifdef CONFIG_DEBUG static char *x86emu_fpu_op_d9_tab[] = { "FLD\tDWORD PTR ", "ESC_D9\t", "FST\tDWORD PTR ", "FSTP\tDWORD PTR ", @@ -89,7 +89,7 @@ static char *x86emu_fpu_op_d9_tab1[] = { "FRNDINT", "FSCALE", "ESC_D9", "ESC_D9", }; -#endif /* DEBUG */ +#endif /* CONFIG_DEBUG */ /* opcode=0xd9 */ void x86emuOp_esc_coprocess_d9(u8 X86EMU_UNUSED(op1)) @@ -100,7 +100,7 @@ void x86emuOp_esc_coprocess_d9(u8 X86EMU_UNUSED(op1)) START_OF_INSTR(); FETCH_DECODE_MODRM(mod, rh, rl); -#ifdef DEBUG +#ifdef CONFIG_DEBUG if (mod != 3) { DECODE_PRINTINSTR32(x86emu_fpu_op_d9_tab, mod, rh, rl); } else { @@ -294,7 +294,7 @@ void x86emuOp_esc_coprocess_d9(u8 X86EMU_UNUSED(op1)) END_OF_INSTR_NO_TRACE(); } -#ifdef DEBUG +#ifdef CONFIG_DEBUG char *x86emu_fpu_op_da_tab[] = { "FIADD\tDWORD PTR ", "FIMUL\tDWORD PTR ", "FICOM\tDWORD PTR ", @@ -316,7 +316,7 @@ char *x86emu_fpu_op_da_tab[] = { "ESC_DA ", "ESC_DA ", "ESC_DA ", "ESC_DA ", }; -#endif /* DEBUG */ +#endif /* CONFIG_DEBUG */ /* opcode=0xda */ void x86emuOp_esc_coprocess_da(u8 X86EMU_UNUSED(op1)) @@ -384,7 +384,7 @@ void x86emuOp_esc_coprocess_da(u8 X86EMU_UNUSED(op1)) END_OF_INSTR_NO_TRACE(); } -#ifdef DEBUG +#ifdef CONFIG_DEBUG char *x86emu_fpu_op_db_tab[] = { "FILD\tDWORD PTR ", "ESC_DB\t19", "FIST\tDWORD PTR ", "FISTP\tDWORD PTR ", @@ -397,7 +397,7 @@ char *x86emu_fpu_op_db_tab[] = { "ESC_DB\t1C", "FLD\tTBYTE PTR ", "ESC_DB\t1E", "FSTP\tTBYTE PTR ", }; -#endif /* DEBUG */ +#endif /* CONFIG_DEBUG */ /* opcode=0xdb */ void x86emuOp_esc_coprocess_db(u8 X86EMU_UNUSED(op1)) @@ -407,7 +407,7 @@ void x86emuOp_esc_coprocess_db(u8 X86EMU_UNUSED(op1)) START_OF_INSTR(); FETCH_DECODE_MODRM(mod, rh, rl); -#ifdef DEBUG +#ifdef CONFIG_DEBUG if (mod != 3) { DECODE_PRINTINSTR32(x86emu_fpu_op_db_tab, mod, rh, rl); } else if (rh == 4) { /* === 11 10 0 nnn */ @@ -428,7 +428,7 @@ void x86emuOp_esc_coprocess_db(u8 X86EMU_UNUSED(op1)) } else { DECODE_PRINTF2("ESC_DB %0x\n", (mod << 6) + (rh << 3) + (rl)); } -#endif /* DEBUG */ +#endif /* CONFIG_DEBUG */ switch (mod) { case 0: destoffset = decode_rm00_address(rl); @@ -504,7 +504,7 @@ void x86emuOp_esc_coprocess_db(u8 X86EMU_UNUSED(op1)) END_OF_INSTR_NO_TRACE(); } -#ifdef DEBUG +#ifdef CONFIG_DEBUG char *x86emu_fpu_op_dc_tab[] = { "FADD\tQWORD PTR ", "FMUL\tQWORD PTR ", "FCOM\tQWORD PTR ", "FCOMP\tQWORD PTR ", @@ -524,7 +524,7 @@ char *x86emu_fpu_op_dc_tab[] = { "FADD\t", "FMUL\t", "FCOM\t", "FCOMP\t", "FSUBR\t", "FSUB\t", "FDIVR\t", "FDIV\t", }; -#endif /* DEBUG */ +#endif /* CONFIG_DEBUG */ /* opcode=0xdc */ void x86emuOp_esc_coprocess_dc(u8 X86EMU_UNUSED(op1)) @@ -618,7 +618,7 @@ void x86emuOp_esc_coprocess_dc(u8 X86EMU_UNUSED(op1)) END_OF_INSTR_NO_TRACE(); } -#ifdef DEBUG +#ifdef CONFIG_DEBUG static char *x86emu_fpu_op_dd_tab[] = { "FLD\tQWORD PTR ", "ESC_DD\t29,", "FST\tQWORD PTR ", "FSTP\tQWORD PTR ", @@ -634,7 +634,7 @@ static char *x86emu_fpu_op_dd_tab[] = { "ESC_DD\t2C,", "ESC_DD\t2D,", "ESC_DD\t2E,", "ESC_DD\t2F,", }; -#endif /* DEBUG */ +#endif /* CONFIG_DEBUG */ /* opcode=0xdd */ void x86emuOp_esc_coprocess_dd(u8 X86EMU_UNUSED(op1)) @@ -718,7 +718,7 @@ void x86emuOp_esc_coprocess_dd(u8 X86EMU_UNUSED(op1)) END_OF_INSTR_NO_TRACE(); } -#ifdef DEBUG +#ifdef CONFIG_DEBUG static char *x86emu_fpu_op_de_tab[] = { @@ -741,7 +741,7 @@ static char *x86emu_fpu_op_de_tab[] = "FSUBRP\t", "FSUBP\t", "FDIVRP\t", "FDIVP\t", }; -#endif /* DEBUG */ +#endif /* CONFIG_DEBUG */ /* opcode=0xde */ void x86emuOp_esc_coprocess_de(u8 X86EMU_UNUSED(op1)) @@ -837,7 +837,7 @@ void x86emuOp_esc_coprocess_de(u8 X86EMU_UNUSED(op1)) END_OF_INSTR_NO_TRACE(); } -#ifdef DEBUG +#ifdef CONFIG_DEBUG static char *x86emu_fpu_op_df_tab[] = { /* mod == 00 */ @@ -860,7 +860,7 @@ static char *x86emu_fpu_op_df_tab[] = { "ESC_DF\t3C,", "ESC_DF\t3D,", "ESC_DF\t3E,", "ESC_DF\t3F," }; -#endif /* DEBUG */ +#endif /* CONFIG_DEBUG */ /* opcode=0xdf */ void x86emuOp_esc_coprocess_df(u8 X86EMU_UNUSED(op1)) diff --git a/util/vgabios/x86emu/src/x86emu/makefile b/util/vgabios/x86emu/src/x86emu/makefile index 3fbc363b34..2a82744e76 100644 --- a/util/vgabios/x86emu/src/x86emu/makefile +++ b/util/vgabios/x86emu/src/x86emu/makefile @@ -32,7 +32,7 @@ # ############################################################################# -.IMPORT .IGNORE: DEBUG +.IMPORT .IGNORE: CONFIG_DEBUG #---------------------------------------------------------------------------- # Define the lists of object files @@ -40,7 +40,7 @@ OBJECTS = sys$O decode$O ops$O ops2$O prim_ops$O fpu$O debug$O CFLAGS += -DSCITECH -.IF $(DEBUG) +.IF $(CONFIG_DEBUG) CFLAGS += -DDEBUG .ENDIF LIBCLEAN = *.dll *.lib *.a diff --git a/util/vgabios/x86emu/src/x86emu/ops.c b/util/vgabios/x86emu/src/x86emu/ops.c index 1b702500a4..b947e60bb8 100644 --- a/util/vgabios/x86emu/src/x86emu/ops.c +++ b/util/vgabios/x86emu/src/x86emu/ops.c @@ -76,7 +76,7 @@ /* constant arrays to do several instructions in just one function */ -#ifdef DEBUG +#ifdef CONFIG_DEBUG static char *x86emu_GenOpName[8] = { "ADD", "OR", "ADC", "SBB", "AND", "SUB", "XOR", "CMP"}; #endif @@ -157,7 +157,7 @@ static u32 (*opcD1_long_operation[])(u32 s, u8 d) = sar_long, }; -#ifdef DEBUG +#ifdef CONFIG_DEBUG static char *opF6_names[8] = { "TEST\t", "", "NOT\t", "NEG\t", "MUL\t", "IMUL\t", "DIV\t", "IDIV\t" }; @@ -1278,7 +1278,7 @@ void x86emuOp_opc80_byte_RM_IMM(u8 X86EMU_UNUSED(op1)) */ START_OF_INSTR(); FETCH_DECODE_MODRM(mod, rh, rl); -#ifdef DEBUG +#ifdef CONFIG_DEBUG if (DEBUG_DECODE()) { /* XXX DECODE_PRINTF may be changed to something more general, so that it is important to leave the strings @@ -1356,7 +1356,7 @@ void x86emuOp_opc81_word_RM_IMM(u8 X86EMU_UNUSED(op1)) */ START_OF_INSTR(); FETCH_DECODE_MODRM(mod, rh, rl); -#ifdef DEBUG +#ifdef CONFIG_DEBUG if (DEBUG_DECODE()) { /* XXX DECODE_PRINTF may be changed to something more general, so that it is important to leave the strings @@ -1472,7 +1472,7 @@ void x86emuOp_opc82_byte_RM_IMM(u8 X86EMU_UNUSED(op1)) */ START_OF_INSTR(); FETCH_DECODE_MODRM(mod, rh, rl); -#ifdef DEBUG +#ifdef CONFIG_DEBUG if (DEBUG_DECODE()) { /* XXX DECODE_PRINTF may be changed to something more general, so that it is important to leave the strings @@ -1548,7 +1548,7 @@ void x86emuOp_opc83_word_RM_IMM(u8 X86EMU_UNUSED(op1)) */ START_OF_INSTR(); FETCH_DECODE_MODRM(mod, rh, rl); -#ifdef DEBUG +#ifdef CONFIG_DEBUG if (DEBUG_DECODE()) { /* XXX DECODE_PRINTF may be changed to something more general, so that it is important to leave the strings @@ -3080,7 +3080,7 @@ void x86emuOp_opcC0_byte_RM_MEM(u8 X86EMU_UNUSED(op1)) */ START_OF_INSTR(); FETCH_DECODE_MODRM(mod, rh, rl); -#ifdef DEBUG +#ifdef CONFIG_DEBUG if (DEBUG_DECODE()) { /* XXX DECODE_PRINTF may be changed to something more general, so that it is important to leave the strings @@ -3155,7 +3155,7 @@ void x86emuOp_opcC1_word_RM_MEM(u8 X86EMU_UNUSED(op1)) */ START_OF_INSTR(); FETCH_DECODE_MODRM(mod, rh, rl); -#ifdef DEBUG +#ifdef CONFIG_DEBUG if (DEBUG_DECODE()) { /* XXX DECODE_PRINTF may be changed to something more general, so that it is important to leave the strings @@ -3632,7 +3632,7 @@ void x86emuOp_opcD0_byte_RM_1(u8 X86EMU_UNUSED(op1)) */ START_OF_INSTR(); FETCH_DECODE_MODRM(mod, rh, rl); -#ifdef DEBUG +#ifdef CONFIG_DEBUG if (DEBUG_DECODE()) { /* XXX DECODE_PRINTF may be changed to something more general, so that it is important to leave the strings @@ -3703,7 +3703,7 @@ void x86emuOp_opcD1_word_RM_1(u8 X86EMU_UNUSED(op1)) */ START_OF_INSTR(); FETCH_DECODE_MODRM(mod, rh, rl); -#ifdef DEBUG +#ifdef CONFIG_DEBUG if (DEBUG_DECODE()) { /* XXX DECODE_PRINTF may be changed to something more general, so that it is important to leave the strings @@ -3805,7 +3805,7 @@ void x86emuOp_opcD2_byte_RM_CL(u8 X86EMU_UNUSED(op1)) */ START_OF_INSTR(); FETCH_DECODE_MODRM(mod, rh, rl); -#ifdef DEBUG +#ifdef CONFIG_DEBUG if (DEBUG_DECODE()) { /* XXX DECODE_PRINTF may be changed to something more general, so that it is important to leave the strings @@ -3878,7 +3878,7 @@ void x86emuOp_opcD3_word_RM_CL(u8 X86EMU_UNUSED(op1)) */ START_OF_INSTR(); FETCH_DECODE_MODRM(mod, rh, rl); -#ifdef DEBUG +#ifdef CONFIG_DEBUG if (DEBUG_DECODE()) { /* XXX DECODE_PRINTF may be changed to something more general, so that it is important to leave the strings @@ -4863,7 +4863,7 @@ void x86emuOp_opcFE_byte_RM(u8 X86EMU_UNUSED(op1)) /* Yet another special case instruction. */ START_OF_INSTR(); FETCH_DECODE_MODRM(mod, rh, rl); -#ifdef DEBUG +#ifdef CONFIG_DEBUG if (DEBUG_DECODE()) { /* XXX DECODE_PRINTF may be changed to something more general, so that it is important to leave the strings @@ -4927,7 +4927,7 @@ void x86emuOp_opcFF_word_RM(u8 X86EMU_UNUSED(op1)) /* Yet another special case instruction. */ START_OF_INSTR(); FETCH_DECODE_MODRM(mod, rh, rl); -#ifdef DEBUG +#ifdef CONFIG_DEBUG if (DEBUG_DECODE()) { /* XXX DECODE_PRINTF may be changed to something more general, so that it is important to leave the strings diff --git a/util/vgabios/x86emu/src/x86emu/x86emu/debug.h b/util/vgabios/x86emu/src/x86emu/x86emu/debug.h index 95a109b261..7bf62c7995 100755 --- a/util/vgabios/x86emu/src/x86emu/x86emu/debug.h +++ b/util/vgabios/x86emu/src/x86emu/x86emu/debug.h @@ -48,7 +48,7 @@ #define CHECK_MEM_ACCESS_F 0x4 /*using regular linear pointer */ #define CHECK_DATA_ACCESS_F 0x8 /*using segment:offset*/ -#ifdef DEBUG +#ifdef CONFIG_DEBUG # define CHECK_IP_FETCH() (M.x86.check & CHECK_IP_FETCH_F) # define CHECK_SP_ACCESS() (M.x86.check & CHECK_SP_ACCESS_F) # define CHECK_MEM_ACCESS() (M.x86.check & CHECK_MEM_ACCESS_F) @@ -60,7 +60,7 @@ # define CHECK_DATA_ACCESS() #endif -#ifdef DEBUG +#ifdef CONFIG_DEBUG # define DEBUG_INSTRUMENT() (M.x86.debug & DEBUG_INSTRUMENT_F) # define DEBUG_DECODE() (M.x86.debug & DEBUG_DECODE_F) # define DEBUG_TRACE() (M.x86.debug & DEBUG_TRACE_F) @@ -99,7 +99,7 @@ # define DEBUG_DECODE_NOPRINT() 0 #endif -#ifdef DEBUG +#ifdef CONFIG_DEBUG # define DECODE_PRINTF(x) if (DEBUG_DECODE()) \ x86emu_decode_printf(x) @@ -129,7 +129,7 @@ # define SAVE_IP_CS(x,y) #endif -#ifdef DEBUG +#ifdef CONFIG_DEBUG #define TRACE_REGS() \ if (DEBUG_DISASSEMBLE()) { \ x86emu_just_disassemble(); \ @@ -140,7 +140,7 @@ # define TRACE_REGS() #endif -#ifdef DEBUG +#ifdef CONFIG_DEBUG # define SINGLE_STEP() if (DEBUG_STEP()) x86emu_single_step() #else # define SINGLE_STEP() @@ -150,7 +150,7 @@ TRACE_REGS(); \ SINGLE_STEP() -#ifdef DEBUG +#ifdef CONFIG_DEBUG # define START_OF_INSTR() # define END_OF_INSTR() EndOfTheInstructionProcedure: x86emu_end_instr(); # define END_OF_INSTR_NO_TRACE() x86emu_end_instr(); @@ -160,7 +160,7 @@ # define END_OF_INSTR_NO_TRACE() #endif -#ifdef DEBUG +#ifdef CONFIG_DEBUG # define CALL_TRACE(u,v,w,x,s) \ if (DEBUG_TRACECALLREGS()) \ x86emu_dump_regs(); \ @@ -176,7 +176,7 @@ # define RETURN_TRACE(n,u,v) #endif -#ifdef DEBUG +#ifdef CONFIG_DEBUG #define DB(x) x #else #define DB(x) -- cgit v1.2.3