From ed993f5faf0c24291f1b61f866d8ea286876e6e8 Mon Sep 17 00:00:00 2001 From: David Wu Date: Mon, 9 Nov 2020 11:13:37 +0800 Subject: lp4x: Add new memory parts and generate SPDs This change adds the following memory parts to LP4x global list of available LP4x parts and to the global JSON file containing LP4x parts and their characteristics. 1. H9HCNNNCRMBLPR-NEE 2. H9HCNNNFBMBLPR-NEE 3. MT53D1G64D4NW-046 WT:A BUG=b:172751925,b:172781673,b:172782100,b:172781562 TEST=cd /util/spd_tools/lp4x && ./gen_spd /src/soc/intel/tigerlake/spd \ global_lp4x_mem_parts.json.txt "TGL" Signed-off-by: David Wu Change-Id: I37702770f707fe078920694468552c5db59c478f Reviewed-on: https://review.coreboot.org/c/coreboot/+/47350 Reviewed-by: Nick Vaccaro Reviewed-by: Paul Fagerburg Reviewed-by: Caveh Jalali Tested-by: build bot (Jenkins) --- util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt | 36 ++++++++++++++++++++++ 1 file changed, 36 insertions(+) (limited to 'util/spd_tools') diff --git a/util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt b/util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt index 109fadb916..91062d0000 100644 --- a/util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt +++ b/util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt @@ -181,6 +181,42 @@ "ranksPerChannel": 2, "speedMbps": 4267 } + }, + { + "name": "H9HCNNNCRMBLPR-NEE", + "attribs": { + "densityPerChannelGb": 8, + "banks": 8, + "channelsPerDie": 2, + "diesPerPackage": 2, + "bitWidthPerChannel": 16, + "ranksPerChannel": 1, + "speedMbps": 4267 + } + }, + { + "name": "H9HCNNNFBMBLPR-NEE", + "attribs": { + "densityPerChannelGb": 8, + "banks": 8, + "channelsPerDie": 2, + "diesPerPackage": 4, + "bitWidthPerChannel": 16, + "ranksPerChannel": 2, + "speedMbps": 4267 + } + }, + { + "name": "MT53D1G64D4NW-046 WT:A", + "attribs": { + "densityPerChannelGb": 16, + "banks": 8, + "channelsPerDie": 2, + "diesPerPackage": 2, + "bitWidthPerChannel": 16, + "ranksPerChannel": 1, + "speedMbps": 4267 + } } ] } -- cgit v1.2.3