From 3f3f53cd5e05eead7a8b8616244a4665bd14b22b Mon Sep 17 00:00:00 2001 From: Raul E Rangel Date: Wed, 6 May 2020 11:47:04 -0600 Subject: util/sconfig: Add LPC and ESPI buses Picasso has an LPC and eSPI bridge on the same PCI DEVFN. They can both be active at the same time. This adds a way to specify which devices belong on which bus. i.e., device pci 14.3 on # - D14F3 bridge device espi 0 on chip ec/google/chromeec device pnp 0c09.0 on end end end device lpc 0 on end end BUG=b:154445472 TEST=Built trembyle and saw static.c contained the espi bus. Signed-off-by: Raul E Rangel Change-Id: I0c2f40813c05680f72e5f30cbb13617e8f994841 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41099 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- util/sconfig/sconfig.l | 2 ++ 1 file changed, 2 insertions(+) (limited to 'util/sconfig/sconfig.l') diff --git a/util/sconfig/sconfig.l b/util/sconfig/sconfig.l index 9fd0cec0e9..5ac5057e23 100755 --- a/util/sconfig/sconfig.l +++ b/util/sconfig/sconfig.l @@ -30,6 +30,8 @@ generic {yylval.number=GENERIC; return(BUS);} mmio {yylval.number=MMIO; return(BUS);} spi {yylval.number=SPI; return(BUS);} usb {yylval.number=USB; return(BUS);} +lpc {yylval.number=LPC; return(BUS);} +espi {yylval.number=ESPI; return(BUS);} irq {yylval.number=IRQ; return(RESOURCE);} drq {yylval.number=DRQ; return(RESOURCE);} io {yylval.number=IO; return(RESOURCE);} -- cgit v1.2.3