From 8fda8f4ac3541441df97d96f4969037ddffd2de7 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Thu, 23 Aug 2018 18:24:32 +0200 Subject: util/romcc: Fix typos Change-Id: Ia9f0f1f527476900e6c54c60508600e16bea786f Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/28293 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- util/romcc/tests/raminit_test.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'util/romcc/tests/raminit_test.c') diff --git a/util/romcc/tests/raminit_test.c b/util/romcc/tests/raminit_test.c index b1baf7e49d..564786b51c 100644 --- a/util/romcc/tests/raminit_test.c +++ b/util/romcc/tests/raminit_test.c @@ -754,7 +754,7 @@ static void spd_set_dramc(void) { /* * Effects: Uses serial presence detect to set the - * DRAMC register, which records if ram is registerd or not, + * DRAMC register, which records if ram is registered or not, * and controls the refresh rate. * The refresh rate is not set here, as memory refresh * cannot be enbaled until after memory is initialized. @@ -997,7 +997,7 @@ static void spd_set_nbxcfg(void) } pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x53, reg); /* Now see if reg is 0xff. If it is we are done. If not, - * we need to set 0x18 into regster 0x50.l + * we need to set 0x18 into register 0x50.l * we will do this in two steps, first or in 0x80 to 0x50.b, * then or in 0x1 to 0x51.b */ -- cgit v1.2.3