From 94501508922c9c7f0c141ce0440f64d800a35a28 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Wed, 19 Oct 2016 17:59:10 +0200 Subject: util/inteltool: Use tabs for indents MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I9d27c276053c51021166f4b22d150060e415d08f Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/17025 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Neuschäfer --- util/inteltool/cpu.c | 136 ++++++++++++++++++++++----------------------- util/inteltool/inteltool.h | 6 +- util/inteltool/pcie.c | 90 +++++++++++++++--------------- 3 files changed, 116 insertions(+), 116 deletions(-) (limited to 'util/inteltool') diff --git a/util/inteltool/cpu.c b/util/inteltool/cpu.c index 9bdc1eb7a0..afafc63647 100644 --- a/util/inteltool/cpu.c +++ b/util/inteltool/cpu.c @@ -815,74 +815,74 @@ int print_intel_core_msrs(void) */ }; - static const msr_entry_t model6_atom_per_core_msrs[] = { - { 0x0006, "IA32_MONITOR_FILTER_SIZE" }, - { 0x0010, "IA32_TIME_STAMP_COUNTER" }, - { 0x001b, "IA32_APIC_BASE" }, - { 0x003a, "IA32_FEATURE_CONTROL" }, - { 0x0040, "MSR_LASTBRANCH_0_FROM_IP" }, - { 0x0041, "MSR_LASTBRANCH_1_FROM_IP" }, - { 0x0042, "MSR_LASTBRANCH_2_FROM_IP" }, - { 0x0043, "MSR_LASTBRANCH_3_FROM_IP" }, - { 0x0044, "MSR_LASTBRANCH_4_FROM_IP" }, - { 0x0045, "MSR_LASTBRANCH_5_FROM_IP" }, - { 0x0046, "MSR_LASTBRANCH_6_FROM_IP" }, - { 0x0047, "MSR_LASTBRANCH_7_FROM_IP" }, - { 0x0060, "MSR_LASTBRANCH_0_TO_IP" }, - { 0x0061, "MSR_LASTBRANCH_1_TO_IP" }, - { 0x0062, "MSR_LASTBRANCH_2_TO_IP" }, - { 0x0063, "MSR_LASTBRANCH_3_TO_IP" }, - { 0x0064, "MSR_LASTBRANCH_4_TO_IP" }, - { 0x0065, "MSR_LASTBRANCH_5_TO_IP" }, - { 0x0066, "MSR_LASTBRANCH_6_TO_IP" }, - { 0x0067, "MSR_LASTBRANCH_7_TO_IP" }, - /* Write register */ - /* - { 0x0079, "IA32_BIOS_UPDT_TRIG" }, - */ - { 0x008b, "IA32_BIOS_SIGN_ID" }, - { 0x00c1, "IA32_PMC0" }, - { 0x00c2, "IA32_PMC1" }, - { 0x00e7, "IA32_MPERF" }, - { 0x00e8, "IA32_APERF" }, - { 0x0174, "IA32_SYSENTER_CS" }, - { 0x0175, "IA32_SYSENTER_ESP" }, - { 0x0176, "IA32_SYSENTER_EIP" }, - { 0x017a, "IA32_MCG_STATUS" }, - { 0x0186, "IA32_PERF_EVNTSEL0" }, - { 0x0187, "IA32_PERF_EVNTSEL1" }, - { 0x0199, "IA32_PERF_CONTROL" }, - { 0x019a, "IA32_CLOCK_MODULATION" }, - { 0x019b, "IA32_THERM_INTERRUPT" }, - { 0x019c, "IA32_THERM_STATUS" }, - { 0x01a0, "IA32_MISC_ENABLES" }, - { 0x01c9, "MSR_LASTBRANCH_TOS" }, - { 0x01d9, "IA32_DEBUGCTL" }, - { 0x01dd, "MSR_LER_FROM_LIP" }, - { 0x01de, "MSR_LER_TO_LIP" }, - { 0x0277, "IA32_PAT" }, - { 0x0309, "IA32_FIXED_CTR0" }, - { 0x030a, "IA32_FIXED_CTR1" }, - { 0x030b, "IA32_FIXED_CTR2" }, - { 0x038d, "IA32_FIXED_CTR_CTRL" }, - { 0x038e, "IA32_PERF_GLOBAL_STATUS" }, - { 0x038f, "IA32_PERF_GLOBAL_CTRL" }, - { 0x0390, "IA32_PERF_GLOBAL_OVF_CTRL" }, - { 0x03f1, "MSR_PEBS_ENABLE" }, - { 0x0480, "IA32_VMX_BASIC" }, - { 0x0481, "IA32_VMX_PINBASED_CTLS" }, - { 0x0482, "IA32_VMX_PROCBASED_CTLS" }, - { 0x0483, "IA32_VMX_EXIT_CTLS" }, - { 0x0484, "IA32_VMX_ENTRY_CTLS" }, - { 0x0485, "IA32_VMX_MISC" }, - { 0x0486, "IA32_VMX_CR0_FIXED0" }, - { 0x0487, "IA32_VMX_CR0_FIXED1" }, - { 0x0488, "IA32_VMX_CR4_FIXED0" }, - { 0x0489, "IA32_VMX_CR4_FIXED1" }, - { 0x048a, "IA32_VMX_VMCS_ENUM" }, - { 0x048b, "IA32_VMX_PROCBASED_CTLS2" }, - { 0x0600, "IA32_DS_AREA" }, - }; + static const msr_entry_t model6_atom_per_core_msrs[] = { + { 0x0006, "IA32_MONITOR_FILTER_SIZE" }, + { 0x0010, "IA32_TIME_STAMP_COUNTER" }, + { 0x001b, "IA32_APIC_BASE" }, + { 0x003a, "IA32_FEATURE_CONTROL" }, + { 0x0040, "MSR_LASTBRANCH_0_FROM_IP" }, + { 0x0041, "MSR_LASTBRANCH_1_FROM_IP" }, + { 0x0042, "MSR_LASTBRANCH_2_FROM_IP" }, + { 0x0043, "MSR_LASTBRANCH_3_FROM_IP" }, + { 0x0044, "MSR_LASTBRANCH_4_FROM_IP" }, + { 0x0045, "MSR_LASTBRANCH_5_FROM_IP" }, + { 0x0046, "MSR_LASTBRANCH_6_FROM_IP" }, + { 0x0047, "MSR_LASTBRANCH_7_FROM_IP" }, + { 0x0060, "MSR_LASTBRANCH_0_TO_IP" }, + { 0x0061, "MSR_LASTBRANCH_1_TO_IP" }, + { 0x0062, "MSR_LASTBRANCH_2_TO_IP" }, + { 0x0063, "MSR_LASTBRANCH_3_TO_IP" }, + { 0x0064, "MSR_LASTBRANCH_4_TO_IP" }, + { 0x0065, "MSR_LASTBRANCH_5_TO_IP" }, + { 0x0066, "MSR_LASTBRANCH_6_TO_IP" }, + { 0x0067, "MSR_LASTBRANCH_7_TO_IP" }, + /* Write register */ + /* + { 0x0079, "IA32_BIOS_UPDT_TRIG" }, + */ + { 0x008b, "IA32_BIOS_SIGN_ID" }, + { 0x00c1, "IA32_PMC0" }, + { 0x00c2, "IA32_PMC1" }, + { 0x00e7, "IA32_MPERF" }, + { 0x00e8, "IA32_APERF" }, + { 0x0174, "IA32_SYSENTER_CS" }, + { 0x0175, "IA32_SYSENTER_ESP" }, + { 0x0176, "IA32_SYSENTER_EIP" }, + { 0x017a, "IA32_MCG_STATUS" }, + { 0x0186, "IA32_PERF_EVNTSEL0" }, + { 0x0187, "IA32_PERF_EVNTSEL1" }, + { 0x0199, "IA32_PERF_CONTROL" }, + { 0x019a, "IA32_CLOCK_MODULATION" }, + { 0x019b, "IA32_THERM_INTERRUPT" }, + { 0x019c, "IA32_THERM_STATUS" }, + { 0x01a0, "IA32_MISC_ENABLES" }, + { 0x01c9, "MSR_LASTBRANCH_TOS" }, + { 0x01d9, "IA32_DEBUGCTL" }, + { 0x01dd, "MSR_LER_FROM_LIP" }, + { 0x01de, "MSR_LER_TO_LIP" }, + { 0x0277, "IA32_PAT" }, + { 0x0309, "IA32_FIXED_CTR0" }, + { 0x030a, "IA32_FIXED_CTR1" }, + { 0x030b, "IA32_FIXED_CTR2" }, + { 0x038d, "IA32_FIXED_CTR_CTRL" }, + { 0x038e, "IA32_PERF_GLOBAL_STATUS" }, + { 0x038f, "IA32_PERF_GLOBAL_CTRL" }, + { 0x0390, "IA32_PERF_GLOBAL_OVF_CTRL" }, + { 0x03f1, "MSR_PEBS_ENABLE" }, + { 0x0480, "IA32_VMX_BASIC" }, + { 0x0481, "IA32_VMX_PINBASED_CTLS" }, + { 0x0482, "IA32_VMX_PROCBASED_CTLS" }, + { 0x0483, "IA32_VMX_EXIT_CTLS" }, + { 0x0484, "IA32_VMX_ENTRY_CTLS" }, + { 0x0485, "IA32_VMX_MISC" }, + { 0x0486, "IA32_VMX_CR0_FIXED0" }, + { 0x0487, "IA32_VMX_CR0_FIXED1" }, + { 0x0488, "IA32_VMX_CR4_FIXED0" }, + { 0x0489, "IA32_VMX_CR4_FIXED1" }, + { 0x048a, "IA32_VMX_VMCS_ENUM" }, + { 0x048b, "IA32_VMX_PROCBASED_CTLS2" }, + { 0x0600, "IA32_DS_AREA" }, + }; static const msr_entry_t model20650_global_msrs[] = { { 0x0000, "IA32_P5_MC_ADDR" }, diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index c6f486fe64..5931cb02c9 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -44,9 +44,9 @@ static inline uint8_t inb(unsigned port) } static inline uint16_t inw(unsigned port) { - uint16_t data; - __asm volatile("inw %w1,%0": "=a" (data) : "d" (port)); - return data; + uint16_t data; + __asm volatile("inw %w1,%0": "=a" (data) : "d" (port)); + return data; } static inline uint32_t inl(unsigned port) { diff --git a/util/inteltool/pcie.c b/util/inteltool/pcie.c index de70e6d294..67b0e1968f 100644 --- a/util/inteltool/pcie.c +++ b/util/inteltool/pcie.c @@ -123,51 +123,51 @@ static const io_register_t sandybridge_dmi_registers[] = { * 329002-002 */ static const io_register_t haswell_ult_dmi_registers[] = { - { 0x00, 4, "DMIVCECH" }, // DMI Virtual Channel Enhanced Capability - { 0x04, 4, "DMIPVCCAP1" }, // DMI Port VC Capability Register 1 - { 0x08, 4, "DMIPVCCAP2" }, // DMI Port VC Capability Register 2 - { 0x0C, 2, "DMI PVCCTL" }, // DMI Port VC Control -/* { 0x0E, 2, "RSVD" }, // Reserved */ - { 0x10, 4, "DMIVC0RCAP" }, // DMI VC0 Resource Capability - { 0x14, 4, "DMIVC0RCTL" }, // DMI VC0 Resource Control -/* { 0x18, 2, "RSVD" }, // Reserved */ - { 0x1A, 2, "DMIVC0RSTS" }, // DMI VC0 Resource Status - { 0x1C, 4, "DMIVC1RCAP" }, // DMI VC1 Resource Capability - { 0x20, 4, "DMIVC1RCTL" }, // DMI VC1 Resource Control -/* { 0x24, 2, "RSVD" }, // Reserved */ - { 0x26, 2, "DMIVC1RSTS" }, // DMI VC1 Resource Status - { 0x28, 4, "DMIVCPRCAP" }, // DMI VCp Resource Capability - { 0x2C, 4, "DMIVCPRCTL" }, // DMI VCp Resource Control -/* { 0x30, 2, "RSVD" }, // Reserved */ - { 0x32, 2, "DMIVCPRSTS" }, // DMI VCp Resource Status - { 0x34, 4, "DMIVCMRCAP" }, // DMI VCm Resource Capability - { 0x38, 4, "DMIVCMRCTL" }, // DMI VCm Resource Control -/* { 0x3C, 2, "RSVD" }, // Reserved */ - { 0x3E, 2, "DMIVCMRSTS" }, // DMI VCm Resource Status - { 0x40, 4, "DMIRCLDECH" }, // DMI Root Complex Link Declaration */ - { 0x44, 4, "DMIESD" }, // DMI Element Self Description -/* { 0x48, 4, "RSVD" }, // Reserved */ -/* { 0x4C, 4, "RSVD" }, // Reserved */ - { 0x50, 4, "DMILE1D" }, // DMI Link Entry 1 Description -/* { 0x54, 4, "RSVD" }, // Reserved */ - { 0x58, 4, "DMILE1A" }, // DMI Link Entry 1 Address - { 0x5C, 4, "DMILUE1A" }, // DMI Link Upper Entry 1 Address - { 0x60, 4, "DMILE2D" }, // DMI Link Entry 2 Description -/* { 0x64, 4, "RSVD" }, // Reserved */ - { 0x68, 4, "DMILE2A" }, // DMI Link Entry 2 Address -/* { 0x6C, 4, "RSVD" }, // Reserved */ -/* { 0x70, 4, "RSVD" }, // Reserved */ -/* { 0x74, 4, "RSVD" }, // Reserved */ -/* { 0x78, 4, "RSVD" }, // Reserved */ -/* { 0x7C, 4, "RSVD" }, // Reserved */ -/* { 0x80, 4, "RSVD" }, // Reserved */ -/* { 0x84, 4, "RSVD" }, // Reserved */ - { 0x88, 2, "LCTL" }, // Link Control - /* ... - Reserved */ - { 0x1C4, 4, "DMIUESTS" }, // DMI Uncorrectable Error Status - { 0x1C8, 4, "DMIUEMSK" }, // DMI Uncorrectable Error Mask - { 0x1D0, 4, "DMICESTS" }, // DMI Correctable Error Status - { 0x1D4, 4, "DMICEMSK" }, // DMI Correctable Error Mask + { 0x00, 4, "DMIVCECH" }, // DMI Virtual Channel Enhanced Capability + { 0x04, 4, "DMIPVCCAP1" }, // DMI Port VC Capability Register 1 + { 0x08, 4, "DMIPVCCAP2" }, // DMI Port VC Capability Register 2 + { 0x0C, 2, "DMI PVCCTL" }, // DMI Port VC Control +/* { 0x0E, 2, "RSVD" }, // Reserved */ + { 0x10, 4, "DMIVC0RCAP" }, // DMI VC0 Resource Capability + { 0x14, 4, "DMIVC0RCTL" }, // DMI VC0 Resource Control +/* { 0x18, 2, "RSVD" }, // Reserved */ + { 0x1A, 2, "DMIVC0RSTS" }, // DMI VC0 Resource Status + { 0x1C, 4, "DMIVC1RCAP" }, // DMI VC1 Resource Capability + { 0x20, 4, "DMIVC1RCTL" }, // DMI VC1 Resource Control +/* { 0x24, 2, "RSVD" }, // Reserved */ + { 0x26, 2, "DMIVC1RSTS" }, // DMI VC1 Resource Status + { 0x28, 4, "DMIVCPRCAP" }, // DMI VCp Resource Capability + { 0x2C, 4, "DMIVCPRCTL" }, // DMI VCp Resource Control +/* { 0x30, 2, "RSVD" }, // Reserved */ + { 0x32, 2, "DMIVCPRSTS" }, // DMI VCp Resource Status + { 0x34, 4, "DMIVCMRCAP" }, // DMI VCm Resource Capability + { 0x38, 4, "DMIVCMRCTL" }, // DMI VCm Resource Control +/* { 0x3C, 2, "RSVD" }, // Reserved */ + { 0x3E, 2, "DMIVCMRSTS" }, // DMI VCm Resource Status + { 0x40, 4, "DMIRCLDECH" }, // DMI Root Complex Link Declaration */ + { 0x44, 4, "DMIESD" }, // DMI Element Self Description +/* { 0x48, 4, "RSVD" }, // Reserved */ +/* { 0x4C, 4, "RSVD" }, // Reserved */ + { 0x50, 4, "DMILE1D" }, // DMI Link Entry 1 Description +/* { 0x54, 4, "RSVD" }, // Reserved */ + { 0x58, 4, "DMILE1A" }, // DMI Link Entry 1 Address + { 0x5C, 4, "DMILUE1A" }, // DMI Link Upper Entry 1 Address + { 0x60, 4, "DMILE2D" }, // DMI Link Entry 2 Description +/* { 0x64, 4, "RSVD" }, // Reserved */ + { 0x68, 4, "DMILE2A" }, // DMI Link Entry 2 Address +/* { 0x6C, 4, "RSVD" }, // Reserved */ +/* { 0x70, 4, "RSVD" }, // Reserved */ +/* { 0x74, 4, "RSVD" }, // Reserved */ +/* { 0x78, 4, "RSVD" }, // Reserved */ +/* { 0x7C, 4, "RSVD" }, // Reserved */ +/* { 0x80, 4, "RSVD" }, // Reserved */ +/* { 0x84, 4, "RSVD" }, // Reserved */ + { 0x88, 2, "LCTL" }, // Link Control + /* ... - Reserved */ + { 0x1C4, 4, "DMIUESTS" }, // DMI Uncorrectable Error Status + { 0x1C8, 4, "DMIUEMSK" }, // DMI Uncorrectable Error Mask + { 0x1D0, 4, "DMICESTS" }, // DMI Correctable Error Status + { 0x1D4, 4, "DMICEMSK" }, // DMI Correctable Error Mask /* ... - Reserved */ }; -- cgit v1.2.3