From 94473afcd29e0f261c54bf2c6a6fc2619d51150b Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Tue, 20 Nov 2018 12:10:29 +0100 Subject: util/inteltool: Add Apollo Lake LPC ID and allow to read PCRs The P2SB (PCI to Side-Band) bridge is on a different PCI device on APL. Hence, we have to decide based on the LPC ID which device to query. Also fix a comment. Change-Id: Ie20d7d2d246629d085bcf4740ba28b1e81e6a12a Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/29896 Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) --- util/inteltool/inteltool.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'util/inteltool/inteltool.h') diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index 5de73aaa05..f2321357b4 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -227,6 +227,8 @@ static inline uint32_t inl(unsigned port) #define PCI_DEVICE_ID_INTEL_BAYTRAIL_GFX 0x0f31 #define CPUID_BAYTRAIL 0x30670 +#define PCI_DEVICE_ID_INTEL_APL_LPC 0x5ae8 + /* Intel starts counting these generations with the integration of the DRAM controller */ #define PCI_DEVICE_ID_INTEL_CORE_0TH_GEN 0xd132 /* Nehalem */ #define PCI_DEVICE_ID_INTEL_CORE_1ST_GEN 0x0044 /* Westmere */ -- cgit v1.2.3