From 0d1366dedcba06264c7215de9f0aac10c7b02f8e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Sat, 14 Mar 2020 22:39:30 +0100 Subject: util/inteltool: add 6th gen. mobile core u/y series MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This adds the 6th gen. mobile core u/y series. Change-Id: I7d802452353afe568e3880765dcd340f0437b392 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/39568 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- util/inteltool/inteltool.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'util/inteltool/inteltool.h') diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index 1c1841c2de..950943f234 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -284,6 +284,8 @@ static inline uint32_t inl(unsigned port) #define PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U 0x0a04 /* Haswell-ULT */ #define PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_U 0x1604 /* Broadwell-ULT */ #define PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D2 0x190f /* Skylake (Desktop) */ +#define PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_U 0x1904 /* Skylake (Mobile) */ +#define PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_Y 0x190c /* Skylake (Mobile) */ #define PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_M 0x1910 /* Skylake (Mobile) */ #define PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST 0x1918 /* Skylake (Workstation) */ #define PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D 0x191f /* Skylake (Desktop) */ -- cgit v1.2.3