From dbc6fcd021759280c71b0e246c0ede34f4879bac Mon Sep 17 00:00:00 2001 From: Stefan Tauner Date: Thu, 20 Jun 2013 18:05:06 +0200 Subject: inteltool: add initial support for Nehalem Also, add pretty printing of Westmere's DMI registers (tested on my t410s by staring at non-zero output values :) Apparently Nehalem does not have a MEMBAR? But there are some documented memory controller control registers in PCI configuration space... left out for now. The PCIEXBAR is not documented publicly AFAICT, but there is a similar register on a device on bus 0xFF. phcoder might know more... Change-Id: I5faadb6e4f701728f5290276c02809b4993bd86d Signed-off-by: Stefan Tauner Reviewed-on: http://review.coreboot.org/3505 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich --- util/inteltool/inteltool.c | 1 + 1 file changed, 1 insertion(+) (limited to 'util/inteltool/inteltool.c') diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index a4edca96df..5cd964a34d 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -71,6 +71,7 @@ static const struct { { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ATOM_DXXX, "Atom D400/500 Series" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ATOM_NXXX, "Atom N400 Series" }, /* Host bridges /DRAM controllers integrated in CPUs */ + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_0TH_GEN, "0th generation (Nehalem family) Core Processor" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_1ST_GEN, "1st generation (Westmere family) Core Processor" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_2ND_GEN, "2nd generation (Sandy Bridge family) Core Processor" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_3RD_GEN, "3rd generation (Ivy Bridge family) Core Processor" }, -- cgit v1.2.3