From ca3548e79fd9005d9e9a5694b438bedd87e70560 Mon Sep 17 00:00:00 2001 From: Pat Erley Date: Wed, 21 Apr 2010 06:23:19 +0000 Subject: This patch adds: ICH6 Southbridge, 82915 Series Northbridge, P4 6xx Series CPU to inteltool Tested on my Clevo D900T, based on ICH6 and i915P, with a p4 630 installed. Signed-off-by: Pat Erley Acked-by: Peter Stuge git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5469 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- util/inteltool/gpio.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) (limited to 'util/inteltool/gpio.c') diff --git a/util/inteltool/gpio.c b/util/inteltool/gpio.c index b4f11691dd..a02817d586 100644 --- a/util/inteltool/gpio.c +++ b/util/inteltool/gpio.c @@ -58,6 +58,24 @@ static const io_register_t ich4_gpio_registers[] = { { 0x3C, 4, "RESERVED" } }; +static const io_register_t ich6_gpio_registers[] = { + { 0x00, 4, "GPIO_USE_SEL" }, + { 0x08, 4, "RESERVED" }, + { 0x0c, 4, "GP_LVL" }, + { 0x10, 4, "RESERVED" }, + { 0x14, 4, "RESERVED" }, + { 0x18, 4, "GPO_BLINK" }, + { 0x1c, 4, "RESERVED" }, + { 0x20, 4, "RESERVED" }, + { 0x24, 4, "RESERVED" }, + { 0x28, 4, "RESERVED" }, + { 0x2c, 4, "GPI_INV" }, + { 0x30, 4, "GPIO_USE_SEL2" }, + { 0x34, 4, "GP_IO_SEL2" }, + { 0x38, 4, "GP_LVL2" }, + { 0x04, 4, "GP_IO_SEL" }, +}; + static const io_register_t ich7_gpio_registers[] = { { 0x00, 4, "GPIO_USE_SEL" }, { 0x04, 4, "GP_IO_SEL" }, @@ -119,6 +137,11 @@ int print_gpios(struct pci_dev *sb) gpio_registers = ich7_gpio_registers; size = ARRAY_SIZE(ich7_gpio_registers); break; + case PCI_DEVICE_ID_INTEL_ICH6: + gpiobase = pci_read_word(sb, 0x48) & 0xfffc; + gpio_registers = ich6_gpio_registers; + size = ARRAY_SIZE(ich6_gpio_registers); + break; case PCI_DEVICE_ID_INTEL_ICH4: case PCI_DEVICE_ID_INTEL_ICH4M: gpiobase = pci_read_word(sb, 0x58) & 0xfffc; -- cgit v1.2.3