From 045d32d78cadc287c5dbd44b8fceba5241772729 Mon Sep 17 00:00:00 2001 From: Uwe Hermann Date: Sun, 26 Oct 2008 18:40:42 +0000 Subject: Add support for the Intel 82371FB PIIX and 82371SB (PIIX3) southbridges. Tested on PIIX3 hardware. Signed-off-by: Uwe Hermann Acked-by: Corey Osgood git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3694 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- util/flashrom/chipset_enable.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) (limited to 'util/flashrom') diff --git a/util/flashrom/chipset_enable.c b/util/flashrom/chipset_enable.c index afac42ed76..85d6e8bd67 100644 --- a/util/flashrom/chipset_enable.c +++ b/util/flashrom/chipset_enable.c @@ -125,6 +125,7 @@ static int enable_flash_piix4(struct pci_dev *dev, const char *name) /* Set bit 9: 1-Meg Extended BIOS Enable (PCI master accesses to * FFF00000-FFF7FFFF are forwarded to ISA). + * Note: This bit is reserved on PIIX/PIIX3. * Set bit 7: Extended BIOS Enable (PCI master accesses to * FFF80000-FFFDFFFF are forwarded to ISA). * Set bit 6: Lower BIOS Enable (PCI master, or ISA master accesses to @@ -134,7 +135,10 @@ static int enable_flash_piix4(struct pci_dev *dev, const char *name) * Note: Accesses to FFFF0000-FFFFFFFF are always forwarded to ISA. * Set bit 2: BIOSCS# Write Enable (1=enable, 0=disable). */ - new = old | 0x02c4; + if (dev->device_id == 0x122e || dev->device_id == 0x7000) + new = old | 0x00c4; /* Bit 9 is reserved on PIIX/PIIX3. */ + else + new = old | 0x02c4; if (new == old) return 0; @@ -745,6 +749,8 @@ typedef struct penable { static const FLASH_ENABLE enables[] = { {0x1039, 0x0630, "SiS630", enable_flash_sis630}, + {0x8086, 0x122e, "Intel PIIX", enable_flash_piix4}, + {0x8086, 0x7000, "Intel PIIX3", enable_flash_piix4}, {0x8086, 0x7110, "Intel PIIX4/4E/4M", enable_flash_piix4}, {0x8086, 0x7198, "Intel 440MX", enable_flash_piix4}, {0x8086, 0x2410, "Intel ICH", enable_flash_ich_4e}, -- cgit v1.2.3