From 3d0303a57c08bf8c56bb55885f6705680097bd27 Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Tue, 7 Dec 2021 17:47:45 +0100 Subject: util/docker/coreboot.org-status: Rewrite parser The current tool is a shell script that mixes data collection and HTML generation and is generally a pain to work with. It takes 15 minutes to run. The new tool is written in go, collects all data first, then generates the output HTML from the data and a single template, and finishes in 10 seconds. The goal in this version is to produce output as similar as possible to the output of the shell script. Some difference will remain because the shell script returns some trash data whose reproduction would require more effort than is worth. Change-Id: I4fab86d24088e4f9eff434c21ce9caa077f3f9e2 Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/59958 Tested-by: build bot (Jenkins) Reviewed-by: Maxim Polyakov --- .../board-status.html/templates/board-status.html | 133 +++++++++++++++++++++ 1 file changed, 133 insertions(+) create mode 100644 util/docker/coreboot.org-status/board-status.html/templates/board-status.html (limited to 'util/docker/coreboot.org-status/board-status.html/templates') diff --git a/util/docker/coreboot.org-status/board-status.html/templates/board-status.html b/util/docker/coreboot.org-status/board-status.html/templates/board-status.html new file mode 100644 index 0000000000..93fcc45101 --- /dev/null +++ b/util/docker/coreboot.org-status/board-status.html/templates/board-status.html @@ -0,0 +1,133 @@ +{{$data := . -}} +{{- define "colorcode" -}} +{{- if eq . "n" }}N{{else + if eq . "y" }}Y{{else + if eq . "" }}?{{else + }}{{.}}{{end -}} +{{end -}} + + + + status report for coreboot boards + + +

Mainboards supported by coreboot

+ +

This page shows two representations of the same data:

+ +

First a list of all mainboards supported by coreboot (current within +one hour) ordered by category. For each mainboard the table shows the +latest user-contributed report of a successful boot on the device.

+ +

After that, the page provides a time-ordered list of these contributed +reports, with the newest report first.

+ +

Boards without such reports may boot or there may be some maintenance +required. The reports contain the coreboot configuration and precise commit +id, so it is possible to reproduce the build.

+ +

We encourage developers and users to contribute reports so we know which +devices are well-tested. We have +a tool in the coreboot repository +to make contributing easy. The data resides in the +board status repository. +Contributing requires an account on review.coreboot.org. After +logging into the site with your preferred OpenID or GitHub/Google +credentials, you can get a user name and password for git pushes on gerrit's +settings screen.

+ +

Sometimes the same board is sold under different names, we've tried to +list all known names but some names might be missing.

+ +

If the board is not found in the coreboot's source code, there might +be some form of support that is not ready yet for inclusion in coreboot, +usually people willing to send their patches to coreboot goes through +gerrit, so looking there could find some +code for boards that are not yet merged.

+ +

Vendor trees

Some vendors have their own coreboot trees/fork, for instance: +

chrome/chromium's tree +

Motherboards supported in coreboot

+ + + + + + + + + + + + + + + + + +{{range $category := .Categories -}} + + + + +{{$color := "#eeeeee" -}} +{{$oldVendor := "" -}} +{{range $b := index $data.BoardsByCategory $category -}} +{{if ne $oldVendor $b.VendorNice}}{{$oldVendor = $b.VendorNice -}} +{{if eq $color "#dddddd"}}{{$color = "#eeeeee"}}{{else}}{{$color = "#dddddd"}}{{end -}} +{{end -}} + + +{{if eq "" (index $data.VendorBoardDate $b.VendorBoard) -}} + +{{- else -}} +{{- $date := index $data.VendorBoardDate $b.VendorBoard -}} + +{{- end}} + + + + + + + +{{template "colorcode" $b.ROMSocketed}} +{{template "colorcode" $b.FlashromSupport}} + +{{end -}} +{{end -}} +

Vendor

Mainboard

Latest known good

Northbridge

Southbridge

Super I/O

CPU

Socket

ROM ¹

P ²

S ³

F ⁴

VCS⁵

{{if $b.BoardURL}}{{$b.VendorNice}}{{else}}{{$b.VendorNice}}{{end}} +{{if $b.Vendor2nd}} ({{$b.Vendor2nd}}) +{{end -}} +

Unknown

{{$b.VendorCooperationScore}} +

+ +¹ ROM chip package (PLCC, DIP32, DIP8, SOIC8).
+² ROM chip protocol/type (parallel flash, LPC, FWH, SPI).
+³ ROM chip socketed (Y/N)?
+⁴ Board supported by [http://www.flashrom.org flashrom] (Y/N)?
+⁵ Vendor Cooperation Score.
+⁶ [http://www.flashrom.org flashrom] does not work when the vendor BIOS is booted, but it does work when the machine is booted with coreboot.
+⁷ Some boards have ROM sockets, others are soldered.
+ +{{range $t := .Timeframes -}} +

+{{range $l := index $data.Logs $t -}} +{{if $l.Reference}} +{{end -}} +{{$l.VendorBoard}} at {{$l.TimeReadable}} +upstream tree ( +{{range $f := $l.Files -}} +{{$f.Basename}} {{/* */}} +{{end -}} +)
+{{- end -}} +{{end -}} +{{/* */}} + + -- cgit v1.2.3

Mainboards supported by coreboot

Vendor trees

Motherboards supported in coreboot

{{index $data.CategoryNiceNames $category}}

{{$t}}