From 7e6946a74c714ff109c35d97001b22c9e868aaea Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Mon, 21 Jan 2019 17:55:02 +0100 Subject: cpu/intel/model_206ax: Remove the notion of sockets With the memory controller the separate sockets becomes a useless distinction. They all used the same code anyway. UNTESTED: This also updates autoport. Change-Id: I044d434a5b8fca75db9eb193c7ffc60f3c78212b Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/31031 Reviewed-by: HAOUAS Elyes Reviewed-by: Tristan Corrick Tested-by: build bot (Jenkins) --- util/autoport/sandybridge.go | 15 ++++----------- 1 file changed, 4 insertions(+), 11 deletions(-) (limited to 'util/autoport') diff --git a/util/autoport/sandybridge.go b/util/autoport/sandybridge.go index 41ac96dc94..4c3bbe87b1 100644 --- a/util/autoport/sandybridge.go +++ b/util/autoport/sandybridge.go @@ -62,16 +62,6 @@ func (i sandybridgemc) Scan(ctx Context, addr PCIDevData) { Chip: "cpu_cluster", Dev: 0, Children: []DevTreeNode{ - { - Chip: "cpu/intel/socket_rPGA989", - Children: []DevTreeNode{ - { - Chip: "lapic", - Dev: 0, - }, - }, - }, - { Chip: "cpu/intel/model_206ax", Comment: "FIXME: check all registers", @@ -85,6 +75,10 @@ func (i sandybridgemc) Scan(ctx Context, addr PCIDevData) { "c3_battery": "5", }, Children: []DevTreeNode{ + { + Chip: "lapic", + Dev: 0, + }, { Chip: "lapic", Dev: 0xacac, @@ -114,7 +108,6 @@ func (i sandybridgemc) Scan(ctx Context, addr PCIDevData) { /* FIXME:XX some configs are unsupported. */ KconfigBool["SANDYBRIDGE_IVYBRIDGE_LVDS"] = true - KconfigBool["CPU_INTEL_SOCKET_RPGA989"] = true KconfigBool["NORTHBRIDGE_INTEL_"+i.variant+"BRIDGE"] = true KconfigBool["USE_NATIVE_RAMINIT"] = true KconfigBool["INTEL_INT15"] = true -- cgit v1.2.3