From 5780d6f3876723b94fbe3653c9d87dad6330862e Mon Sep 17 00:00:00 2001 From: Paul Menzel Date: Wed, 14 Jan 2015 16:53:05 +0100 Subject: Revert "vboot2: add verstage" This reverts commit 320647abdad1ea6cdceb834933507677020ea388, because it introduced the following regression. $ LANG=C make V=1 Warning: no suitable GCC for arm. Warning: no suitable GCC for aarch64. Warning: no suitable GCC for riscv. /bin/sh: --: invalid option Usage: /bin/sh [GNU long option] [option] ... /bin/sh [GNU long option] [option] script-file ... GNU long options: --debug --debugger --dump-po-strings --dump-strings --help --init-file --login --noediting --noprofile --norc --posix --rcfile --restricted --verbose --version Shell options: -ilrsD or -c command or -O shopt_option (invocation only) -abefhkmnptuvxBCHP or -o option make: -print-libgcc-file-name: Command not found It also introduced trailing whitespace. Change-Id: I50ec00a38e24c854fa926357cd24f9286bf4f66f Signed-off-by: Paul Menzel Reviewed-on: http://review.coreboot.org/8223 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc Reviewed-by: Edward O'Callaghan --- toolchain.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'toolchain.inc') diff --git a/toolchain.inc b/toolchain.inc index bd8da83366..b54d95935b 100644 --- a/toolchain.inc +++ b/toolchain.inc @@ -51,7 +51,7 @@ HOSTCXX:=CCC_CXX="$(HOSTCXX)" $(CXX) ROMCC=CCC_CC="$(ROMCC_BIN)" $(CC) endif -COREBOOT_STANDARD_STAGES := bootblock verstage romstage ramstage +COREBOOT_STANDARD_STAGES := bootblock romstage ramstage ARCHDIR-i386 := x86 ARCHDIR-x86_32 := x86 -- cgit v1.2.3