From deabf510bff37c1f3a1fd3ec50b88db17d38b802 Mon Sep 17 00:00:00 2001 From: Peter Stuge Date: Thu, 10 May 2007 23:50:27 +0000 Subject: Changes by Richard Smith and Peter Stuge from the LinuxBIOS symposium 2006. With CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=0, 1 million outb():s are used for timer calibration, which takes about one second. All EPIA-M boards have timer2 so we use it to boot faster. Only some EPIA boards have the Nehemiah CPU with timer2 so we default to IO calibration but add the TSC options so that they can be set in Config.lb. src/mainboard/via/epia*/reset.c is dead code (entire file within #if 0) so we set HAVE_HARD_RESET=0 for both boards. Signed-off-by: Peter Stuge Acked-by: Stefan Reinauer git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2659 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- targets/via/epia/Config.lb | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'targets/via') diff --git a/targets/via/epia/Config.lb b/targets/via/epia/Config.lb index e45fcf33d0..39f1a6b377 100644 --- a/targets/via/epia/Config.lb +++ b/targets/via/epia/Config.lb @@ -1,6 +1,11 @@ # Sample config file for EPIA # This will make a target directory of ./epia +## uncomment these three lines if you have a Nehemiah CPU to boot 1s faster +#option CONFIG_UDELAY_IO=0 +#option CONFIG_UDELAY_TSC=1 +#option CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 + target epia mainboard via/epia option MAXIMUM_CONSOLE_LOGLEVEL=9 -- cgit v1.2.3