From ffe58107df667b5142e3c3efd25c1ee3360038bf Mon Sep 17 00:00:00 2001 From: Rizwan Qureshi Date: Fri, 10 Feb 2017 15:58:24 +0530 Subject: soc/intel/skylake: Add option to disable host reads to PMC XRAM FSP disables host access to shadowed PMC XRAM registers by default, it also provides a UPD to enable/disable host reads to these regiters. Expose the same in devicetree as a config option. Change-Id: Iaa33aa3233bda4f050da37d1d8af0556311c9496 Signed-off-by: Rizwan Qureshi Reviewed-on: https://review.coreboot.org/18319 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/intel/skylake/chip.h | 3 +++ src/soc/intel/skylake/chip_fsp20.c | 3 +++ 2 files changed, 6 insertions(+) (limited to 'src') diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 445dcb67c1..fbd10a918c 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -402,6 +402,9 @@ struct soc_intel_skylake_config { */ u32 PrmrrSize; + /* Enable/Disable host reads to PMC XRAM registers */ + u8 PchPmPmcReadDisable; + /* Statically clock gate 8254 PIT. */ u8 clock_gate_8254; diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index 851c957624..2d9b864629 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -258,6 +258,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->FastPkgCRampDisableGt = config->FastPkgCRampDisableGt; params->FastPkgCRampDisableSa = config->FastPkgCRampDisableSa; + /* Enable PMC XRAM read */ + tconfig->PchPmPmcReadDisable = config->PchPmPmcReadDisable; + soc_irq_settings(params); } -- cgit v1.2.3