From ffc87e9cbe1a811332de6a87186e9c3ad3755709 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Fri, 29 Jan 2021 16:14:57 +0100 Subject: soc/amd/cezanne: add use result of acpi_is_wakeup_s3() in FSP calls MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cezanne doesn't have ACPI support yet, but in this case the function always returns 0, so it can already be used. Signed-off-by: Felix Held Change-Id: I1f5e1f31bf1e52988fcef90daf7b93169e21cbb1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50126 Reviewed-by: Kyösti Mälkki Tested-by: build bot (Jenkins) --- src/soc/amd/cezanne/chip.c | 3 ++- src/soc/amd/cezanne/romstage.c | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/soc/amd/cezanne/chip.c b/src/soc/amd/cezanne/chip.c index fd930896a7..4a39024b1b 100644 --- a/src/soc/amd/cezanne/chip.c +++ b/src/soc/amd/cezanne/chip.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include @@ -12,7 +13,7 @@ static void enable_dev(struct device *dev) static void soc_init(void *chip_info) { - fsp_silicon_init(false); /* no S3 support yet */ + fsp_silicon_init(acpi_is_wakeup_s3()); fch_init(chip_info); } diff --git a/src/soc/amd/cezanne/romstage.c b/src/soc/amd/cezanne/romstage.c index 509addfa52..f790def747 100644 --- a/src/soc/amd/cezanne/romstage.c +++ b/src/soc/amd/cezanne/romstage.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include @@ -19,7 +20,7 @@ asmlinkage void car_stage_entry(void) u32 val = cpuid_eax(1); printk(BIOS_DEBUG, "Family_Model: %08x\n", val); - fsp_memory_init(false); /* no S3 resume yet */ + fsp_memory_init(acpi_is_wakeup_s3()); run_ramstage(); } -- cgit v1.2.3