From ffb83bee2627f1e33f8302a3e630e036e93891a9 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subrata.banik@intel.com>
Date: Mon, 29 Apr 2019 13:58:43 +0530
Subject: soc/intel/icelake: Select FSP_M_XIP

This patch ports CB:32275 changes from CNL to ICL.

Ice Lake require that FSP-M component should be
XIP. This change selects FSP_M_XIP so that the right arguments are
passed into cbfstool when adding this component.

Change-Id: Icc5550f1f94957fa1b28c8bba6fc0efee98e233e
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32507
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/icelake/Kconfig | 1 +
 1 file changed, 1 insertion(+)

(limited to 'src')

diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig
index 2fbc6da15f..a4b46baab5 100644
--- a/src/soc/intel/icelake/Kconfig
+++ b/src/soc/intel/icelake/Kconfig
@@ -19,6 +19,7 @@ config CPU_SPECIFIC_OPTIONS
 	select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
 	select COMMON_FADT
 	select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
+	select FSP_M_XIP
 	select GENERIC_GPIO_LIB
 	select HAVE_FSP_GOP
 	select INTEL_DESCRIPTOR_MODE_CAPABLE
-- 
cgit v1.2.3