From fec6fa799ce16eabec0add9bfe6ab5222921f612 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Wed, 12 Jul 2017 16:30:47 +0300 Subject: vendorcode/amd/agesa: Tidy up gcccar.inc MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change register preservations and fix comments about register usage accordingly. Do this to avoid use of %mm0-2 registers inside macros defined in gcccar.inc, as future implementation of C_BOOTBLOCK_ENVIRONMENT will use them as well. Adjust caller side accordingly. Change-Id: Ic76fcc31ae714baf5259d17c41b62a3610aa947b Signed-off-by: Marshall Dawson Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/20579 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones --- src/cpu/amd/agesa/cache_as_ram.inc | 13 +++++-------- src/vendorcode/amd/agesa/f10/gcccar.inc | 23 +++++------------------ src/vendorcode/amd/agesa/f12/gcccar.inc | 23 +++++------------------ src/vendorcode/amd/agesa/f14/gcccar.inc | 23 +++++------------------ src/vendorcode/amd/agesa/f15/gcccar.inc | 23 +++++------------------ src/vendorcode/amd/agesa/f15tn/gcccar.inc | 23 +++++------------------ src/vendorcode/amd/agesa/f16kb/gcccar.inc | 23 +++++------------------ 7 files changed, 35 insertions(+), 116 deletions(-) (limited to 'src') diff --git a/src/cpu/amd/agesa/cache_as_ram.inc b/src/cpu/amd/agesa/cache_as_ram.inc index 8038177c7c..cfad2f7d1a 100644 --- a/src/cpu/amd/agesa/cache_as_ram.inc +++ b/src/cpu/amd/agesa/cache_as_ram.inc @@ -32,7 +32,7 @@ cache_as_ram_setup: /* Preserve BIST. */ - movl %eax, %ebp + movd %eax, %mm0 post_code(0xa0) @@ -45,7 +45,6 @@ cache_as_ram_setup: post_code(0xa1) - /* NOTE: %ebx, %ebp are preserved in AMD_ENABLE_STACK. */ AMD_ENABLE_STACK /* Align the stack. */ @@ -96,19 +95,18 @@ cache_as_ram_setup: #endif - /* Calling conventions preserve BIST in %ebp. */ - call early_all_cores /* Must maintain 16-byte stack alignment here. */ pushl $0x0 pushl $0x0 pushl $0x0 - pushl %ebp + movd %mm0, %eax /* bist */ + pushl %eax call romstage_main - movl %eax, %ebx + movl %eax, %esp -/* Register %ebx is new stacktop for remaining of romstage. +/* Register %esp is new stacktop for remaining of romstage. * It is the only register preserved in AMD_DISABLE_STACK. */ @@ -125,7 +123,6 @@ disable_cache_as_ram: andl $0x9fffffff, %eax movl %eax, %cr0 - movl %ebx, %esp call romstage_after_car /* Should never see this postcode */ diff --git a/src/vendorcode/amd/agesa/f10/gcccar.inc b/src/vendorcode/amd/agesa/f10/gcccar.inc index c490a61d58..8d085ad708 100644 --- a/src/vendorcode/amd/agesa/f10/gcccar.inc +++ b/src/vendorcode/amd/agesa/f10/gcccar.inc @@ -1201,7 +1201,7 @@ node_core_f15_exit: * AMD_ENABLE_STACK: Setup a stack * * In: -* EBX = Return address (preserved) +* No inputs * * Out: * SS:ESP - Our new private stack location @@ -1212,11 +1212,8 @@ node_core_f15_exit: * * Requirements: * * This routine presently is limited to a max of 64 processor cores -* Preserved: -* ebx ebp * Destroyed: -* eax, ecx, edx, edi, esi, ds, es, ss, esp -* mmx0, mmx1 +* EBX, EDX, EDI, ESI, EBP, DS, ES * * Description: * Fixed MTRR address allocation to cores: @@ -1276,8 +1273,6 @@ node_core_f15_exit: # Note that SS:ESP will be default stack. Note that this stack # routine will not be used after memory has been initialized. Because # of its limited lifetime, it will not conflict with typical PCI devices. - movd %ebx, %mm0 # Put return address in a safe place - movd %ebp, %mm1 # Save some other user registers # get node id and core id of current executing core GET_NODE_ID_CORE_ID # Sets ESI[23:16]=Shared core## SI[15,8]= Node## SI[7,0]= core# (relative to node) @@ -1589,9 +1584,6 @@ ClearTheStack: # Stack base is in SS, stack pointer is or $0x40000000, %eax # eax = AGESA_WARNING (Stack has already been set up) #.endif 0: - - movd %mm0, %ebx # Restore return address - movd %mm1, %ebp .endm /***************************************************************************** @@ -1611,17 +1603,15 @@ ClearTheStack: # Stack base is in SS, stack pointer is * none * * Out: -* EAX = AGESA_SUCCESS +* none * * Preserved: -* ebx +* ESP * Destroyed: -* eax, ecx, edx, esp +* EAX, EBX, ECX, EDX, EDI, ESI *****************************************************************************/ .macro AMD_DISABLE_STACK - mov %ebx, %esp # Save return address - # get node/core/flags of current executing core GET_NODE_ID_CORE_ID # Sets ESI[15,8]= Node#; ESI[7,0]= core# (relative to node) @@ -1647,7 +1637,4 @@ ClearTheStack: # Stack base is in SS, stack pointer is AMD_DISABLE_STACK_FAMILY_HOOK # Re-Enable 'normal' cache operations - mov %esp, %ebx - xor %eax, %eax - .endm diff --git a/src/vendorcode/amd/agesa/f12/gcccar.inc b/src/vendorcode/amd/agesa/f12/gcccar.inc index ca281725c7..6a8045198d 100644 --- a/src/vendorcode/amd/agesa/f12/gcccar.inc +++ b/src/vendorcode/amd/agesa/f12/gcccar.inc @@ -1181,7 +1181,7 @@ node_core_f15_exit: * AMD_ENABLE_STACK: Setup a stack * * In: -* EBX = Return address (preserved) +* No inputs * * Out: * SS:ESP - Our new private stack location @@ -1192,11 +1192,8 @@ node_core_f15_exit: * * Requirements: * * This routine presently is limited to a max of 64 processor cores -* Preserved: -* ebx ebp * Destroyed: -* eax, ecx, edx, edi, esi, ds, es, ss, esp -* mmx0, mmx1 +* EBX, EDX, EDI, ESI, EBP, DS, ES * * Description: * Fixed MTRR address allocation to cores: @@ -1256,8 +1253,6 @@ node_core_f15_exit: # Note that SS:ESP will be default stack. Note that this stack # routine will not be used after memory has been initialized. Because # of its limited lifetime, it will not conflict with typical PCI devices. - movd %ebx, %mm0 # Put return address in a safe place - movd %ebp, %mm1 # Save some other user registers # get node id and core id of current executing core GET_NODE_ID_CORE_ID # Sets ESI[23:16]=Shared core## SI[15,8]= Node## SI[7,0]= core# (relative to node) @@ -1569,9 +1564,6 @@ ClearTheStack: # Stack base is in SS, stack pointer is or $0x40000000, %eax # eax = AGESA_WARNING (Stack has already been set up) #.endif 0: - - movd %mm0, %ebx # Restore return address - movd %mm1, %ebp .endm /***************************************************************************** @@ -1582,17 +1574,15 @@ ClearTheStack: # Stack base is in SS, stack pointer is * none * * Out: -* EAX = AGESA_SUCCESS +* none * * Preserved: -* ebx +* ESP * Destroyed: -* eax, ecx, edx, esp +* EAX, EBX, ECX, EDX, EDI, ESI *****************************************************************************/ .macro AMD_DISABLE_STACK - mov %ebx, %esp # Save return address - # get node/core/flags of current executing core GET_NODE_ID_CORE_ID # Sets ESI[15,8]= Node#; ESI[7,0]= core# (relative to node) @@ -1618,7 +1608,4 @@ ClearTheStack: # Stack base is in SS, stack pointer is AMD_DISABLE_STACK_FAMILY_HOOK # Re-Enable 'normal' cache operations - mov %esp, %ebx - xor %eax, %eax - .endm diff --git a/src/vendorcode/amd/agesa/f14/gcccar.inc b/src/vendorcode/amd/agesa/f14/gcccar.inc index 18376dfaf2..95dd74d6cb 100644 --- a/src/vendorcode/amd/agesa/f14/gcccar.inc +++ b/src/vendorcode/amd/agesa/f14/gcccar.inc @@ -1181,7 +1181,7 @@ node_core_f15_exit: * AMD_ENABLE_STACK: Setup a stack * * In: -* EBX = Return address (preserved) +* No inputs * * Out: * SS:ESP - Our new private stack location @@ -1192,11 +1192,8 @@ node_core_f15_exit: * * Requirements: * * This routine presently is limited to a max of 64 processor cores -* Preserved: -* ebx ebp * Destroyed: -* eax, ecx, edx, edi, esi, ds, es, ss, esp -* mmx0, mmx1 +* EBX, EDX, EDI, ESI, EBP, DS, ES * * Description: * Fixed MTRR address allocation to cores: @@ -1256,8 +1253,6 @@ node_core_f15_exit: # Note that SS:ESP will be default stack. Note that this stack # routine will not be used after memory has been initialized. Because # of its limited lifetime, it will not conflict with typical PCI devices. - movd %ebx, %mm0 # Put return address in a safe place - movd %ebp, %mm1 # Save some other user registers # get node id and core id of current executing core GET_NODE_ID_CORE_ID # Sets ESI[23:16]=Shared core## SI[15,8]= Node## SI[7,0]= core# (relative to node) @@ -1569,9 +1564,6 @@ ClearTheStack: # Stack base is in SS, stack pointer is or $0x40000000, %eax # eax = AGESA_WARNING (Stack has already been set up) #.endif 0: - - movd %mm0, %ebx # Restore return address - movd %mm1, %ebp .endm /***************************************************************************** @@ -1582,17 +1574,15 @@ ClearTheStack: # Stack base is in SS, stack pointer is * none * * Out: -* EAX = AGESA_SUCCESS +* none * * Preserved: -* ebx +* ESP * Destroyed: -* eax, ecx, edx, esp +* EAX, EBX, ECX, EDX, EDI, ESI *****************************************************************************/ .macro AMD_DISABLE_STACK - mov %ebx, %esp # Save return address - # get node/core/flags of current executing core GET_NODE_ID_CORE_ID # Sets ESI[15,8]= Node#; ESI[7,0]= core# (relative to node) @@ -1618,7 +1608,4 @@ ClearTheStack: # Stack base is in SS, stack pointer is AMD_DISABLE_STACK_FAMILY_HOOK # Re-Enable 'normal' cache operations - mov %esp, %ebx - xor %eax, %eax - .endm diff --git a/src/vendorcode/amd/agesa/f15/gcccar.inc b/src/vendorcode/amd/agesa/f15/gcccar.inc index 4d00df392d..427c7e5622 100644 --- a/src/vendorcode/amd/agesa/f15/gcccar.inc +++ b/src/vendorcode/amd/agesa/f15/gcccar.inc @@ -1216,7 +1216,7 @@ node_core_f15_exit: * AMD_ENABLE_STACK: Setup a stack * * In: -* EBX = Return address (preserved) +* No inputs * * Out: * SS:ESP - Our new private stack location @@ -1227,11 +1227,8 @@ node_core_f15_exit: * * Requirements: * * This routine presently is limited to a max of 64 processor cores -* Preserved: -* ebx ebp * Destroyed: -* eax, ecx, edx, edi, esi, ds, es, ss, esp -* mmx0, mmx1 +* EBX, EDX, EDI, ESI, EBP, DS, ES * * Description: * Fixed MTRR address allocation to cores: @@ -1291,8 +1288,6 @@ node_core_f15_exit: # Note that SS:ESP will be default stack. Note that this stack # routine will not be used after memory has been initialized. Because # of its limited lifetime, it will not conflict with typical PCI devices. - movd %ebx, %mm0 # Put return address in a safe place - movd %ebp, %mm1 # Save some other user registers # get node id and core id of current executing core GET_NODE_ID_CORE_ID # Sets ESI[23:16]=Shared core## SI[15,8]= Node## SI[7,0]= core# (relative to node) @@ -1604,9 +1599,6 @@ ClearTheStack: # Stack base is in SS, stack pointer is or $0x40000000, %eax # eax = AGESA_WARNING (Stack has already been set up) #.endif 0: - - movd %mm0, %ebx # Restore return address - movd %mm1, %ebp .endm /***************************************************************************** @@ -1626,17 +1618,15 @@ ClearTheStack: # Stack base is in SS, stack pointer is * none * * Out: -* EAX = AGESA_SUCCESS +* none * * Preserved: -* ebx +* ESP * Destroyed: -* eax, ecx, edx, esp +* EAX, EBX, ECX, EDX, EDI, ESI *****************************************************************************/ .macro AMD_DISABLE_STACK - mov %ebx, %esp # Save return address - # get node/core/flags of current executing core GET_NODE_ID_CORE_ID # Sets ESI[15,8]= Node#; ESI[7,0]= core# (relative to node) @@ -1662,7 +1652,4 @@ ClearTheStack: # Stack base is in SS, stack pointer is AMD_DISABLE_STACK_FAMILY_HOOK # Re-Enable 'normal' cache operations - mov %esp, %ebx - xor %eax, %eax - .endm diff --git a/src/vendorcode/amd/agesa/f15tn/gcccar.inc b/src/vendorcode/amd/agesa/f15tn/gcccar.inc index 4f1e7a0b25..7ac9613fca 100644 --- a/src/vendorcode/amd/agesa/f15tn/gcccar.inc +++ b/src/vendorcode/amd/agesa/f15tn/gcccar.inc @@ -1511,7 +1511,7 @@ node_core_f15_exit: * AMD_ENABLE_STACK: Setup a stack * * In: -* EBX = Return address (preserved) +* No inputs * * Out: * SS:ESP - Our new private stack location @@ -1522,11 +1522,8 @@ node_core_f15_exit: * * Requirements: * * This routine presently is limited to a max of 64 processor cores -* Preserved: -* ebx ebp * Destroyed: -* eax, ecx, edx, edi, esi, ds, es, ss, esp -* mmx0, mmx1 +* EBX, EDX, EDI, ESI, EBP, DS, ES * * Description: * Fixed MTRR address allocation to cores: @@ -1586,8 +1583,6 @@ node_core_f15_exit: # Note that SS:ESP will be default stack. Note that this stack # routine will not be used after memory has been initialized. Because # of its limited lifetime, it will not conflict with typical PCI devices. - movd %ebx, %mm0 # Put return address in a safe place - movd %ebp, %mm1 # Save some other user registers # get node id and core id of current executing core GET_NODE_ID_CORE_ID # Sets ESI[23:16]=Shared core## SI[15,8]= Node## SI[7,0]= core# (relative to node) @@ -1899,9 +1894,6 @@ ClearTheStack: # Stack base is in SS, stack pointer is or $0x40000000, %eax # eax = AGESA_WARNING (Stack has already been set up) #.endif 0: - - movd %mm0, %ebx # Restore return address - movd %mm1, %ebp .endm /***************************************************************************** @@ -1921,17 +1913,15 @@ ClearTheStack: # Stack base is in SS, stack pointer is * none * * Out: -* EAX = AGESA_SUCCESS +* none * * Preserved: -* ebx +* ESP * Destroyed: -* eax, ecx, edx, esp +* EAX, EBX, ECX, EDX, EDI, ESI *****************************************************************************/ .macro AMD_DISABLE_STACK - mov %ebx, %esp # Save return address - # get node/core/flags of current executing core GET_NODE_ID_CORE_ID # Sets ESI[15,8]= Node#; ESI[7,0]= core# (relative to node) @@ -1957,7 +1947,4 @@ ClearTheStack: # Stack base is in SS, stack pointer is AMD_DISABLE_STACK_FAMILY_HOOK # Re-Enable 'normal' cache operations - mov %esp, %ebx - xor %eax, %eax - .endm diff --git a/src/vendorcode/amd/agesa/f16kb/gcccar.inc b/src/vendorcode/amd/agesa/f16kb/gcccar.inc index bd670590a7..26e61da34b 100644 --- a/src/vendorcode/amd/agesa/f16kb/gcccar.inc +++ b/src/vendorcode/amd/agesa/f16kb/gcccar.inc @@ -874,7 +874,7 @@ node_core_f16_exit: * AMD_ENABLE_STACK: Setup a stack * * In: -* EBX = Return address (preserved) +* No inputs * * Out: * SS:ESP - Our new private stack location @@ -885,11 +885,8 @@ node_core_f16_exit: * * Requirements: * * This routine presently is limited to a max of 64 processor cores -* Preserved: -* ebx ebp * Destroyed: -* eax, ecx, edx, edi, esi, ds, es, ss, esp -* mmx0, mmx1 +* EBX, EDX, EDI, ESI, EBP, DS, ES * * Description: * Fixed MTRR address allocation to cores: @@ -949,8 +946,6 @@ node_core_f16_exit: # Note that SS:ESP will be default stack. Note that this stack # routine will not be used after memory has been initialized. Because # of its limited lifetime, it will not conflict with typical PCI devices. - movd %ebx, %mm0 # Put return address in a safe place - movd %ebp, %mm1 # Save some other user registers # get node id and core id of current executing core GET_NODE_ID_CORE_ID # Sets ESI[23:16]=Shared core## SI[15,8]= Node## SI[7,0]= core# (relative to node) @@ -1262,9 +1257,6 @@ ClearTheStack: # Stack base is in SS, stack pointer is or $0x40000000, %eax # eax = AGESA_WARNING (Stack has already been set up) #.endif 0: - - movd %mm0, %ebx # Restore return address - movd %mm1, %ebp .endm /***************************************************************************** @@ -1284,17 +1276,15 @@ ClearTheStack: # Stack base is in SS, stack pointer is * none * * Out: -* EAX = AGESA_SUCCESS +* none * * Preserved: -* ebx +* ESP * Destroyed: -* eax, ecx, edx, esp +* EAX, EBX, ECX, EDX, EDI, ESI *****************************************************************************/ .macro AMD_DISABLE_STACK - mov %ebx, %esp # Save return address - # get node/core/flags of current executing core GET_NODE_ID_CORE_ID # Sets ESI[15,8]= Node#; ESI[7,0]= core# (relative to node) @@ -1320,7 +1310,4 @@ ClearTheStack: # Stack base is in SS, stack pointer is AMD_DISABLE_STACK_FAMILY_HOOK # Re-Enable 'normal' cache operations - mov %esp, %ebx - xor %eax, %eax - .endm -- cgit v1.2.3