From fc3741f379f972d9d7d962fa4e62cec7a01f5e86 Mon Sep 17 00:00:00 2001 From: Lee Leahy Date: Thu, 26 May 2016 17:12:17 -0700 Subject: Add Board Checklist Support Build the _checklist.html file which contains a checklist table for each stage of coreboot. This processing builds a set of implemented (done) routines which are marked green in the table. The remaining required routines (work-to-do) are marked red in the table and the optional routines are marked yellow in the table. The table heading for each stage contains a completion percentage in terms of count of routines (done .vs. required). Add some Kconfig values: * CREATE_BOARD_CHECKLIST - When selected creates the checklist file * MAKE_CHECKLIST_PUBLIC - Copies the checklist file into the Documenation directory * CHECKLIST_DATA_FILE_LOCATION - Location of the checklist data files: * _complete.dat - Lists all of the weak routines * _optional.dat - Lists weak routines which may be optionally implemented TEST=Build with Galileo Gen2. Change-Id: Ie056f8bb6d45ff7f3bc6390b5630b5063f54c527 Signed-off-by: Lee Leahy Reviewed-on: https://review.coreboot.org/15011 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/Kconfig | 30 +++++++++ src/drivers/intel/fsp1_1/Kconfig | 4 ++ .../fsp/fsp1_1/checklist/bootblock_complete.dat | 77 ++++++++++++++++++++++ .../fsp/fsp1_1/checklist/ramstage_complete.dat | 53 +++++++++++++++ .../fsp/fsp1_1/checklist/ramstage_optional.dat | 46 +++++++++++++ .../fsp/fsp1_1/checklist/romstage_complete.dat | 54 +++++++++++++++ .../fsp/fsp1_1/checklist/romstage_optional.dat | 34 ++++++++++ .../fsp/fsp1_1/checklist/verstage_complete.dat | 35 ++++++++++ .../fsp/fsp1_1/checklist/verstage_optional.dat | 22 +++++++ 9 files changed, 355 insertions(+) create mode 100644 src/vendorcode/intel/fsp/fsp1_1/checklist/bootblock_complete.dat create mode 100644 src/vendorcode/intel/fsp/fsp1_1/checklist/ramstage_complete.dat create mode 100644 src/vendorcode/intel/fsp/fsp1_1/checklist/ramstage_optional.dat create mode 100644 src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_complete.dat create mode 100644 src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_optional.dat create mode 100644 src/vendorcode/intel/fsp/fsp1_1/checklist/verstage_complete.dat create mode 100644 src/vendorcode/intel/fsp/fsp1_1/checklist/verstage_optional.dat (limited to 'src') diff --git a/src/Kconfig b/src/Kconfig index 6e6e9447ff..4eda5378f9 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -1174,3 +1174,33 @@ config DEBUG_BOOT_STATE help Control debugging of the boot state machine. When selected displays the state boundaries in ramstage. + +config CREATE_BOARD_CHECKLIST + bool + default n + help + When selected, creates a webpage showing the implementation status for + the board. Routines highlighted in green are complete, yellow are + optional and red are required and must be implemented. A table is + produced for each stage of the boot process except the bootblock. The + red items may be used as an implementation checklist for the board. + +config MAKE_CHECKLIST_PUBLIC + bool + default n + help + When selected, build/$(CONFIG_MAINBOARD_PART_NUMBER)_checklist.html + is copied into the Documentation/$(CONFIG_MAINBOARD_VENDOR)/Board + directory. + +config CHECKLIST_DATA_FILE_LOCATION + string + help + Location of the _complete.dat and _optional.dat files + that are consumed during checklist processing. _complete.dat + contains the symbols that are expected to be in the resulting image. + _optional.dat is a subset of _complete.dat and contains + a list of weak symbols which the resulting image may consume. Other + symbols contained only in _complete.dat will be flagged as + required and not implemented if a weak implementation is found in the + resulting image. diff --git a/src/drivers/intel/fsp1_1/Kconfig b/src/drivers/intel/fsp1_1/Kconfig index 9b2c463878..86f6c7b99e 100644 --- a/src/drivers/intel/fsp1_1/Kconfig +++ b/src/drivers/intel/fsp1_1/Kconfig @@ -115,4 +115,8 @@ config VBT_FILE depends on GOP_SUPPORT default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/vbt.bin" +config CHECKLIST_DATA_FILE_LOCATION + string + default "src/vendorcode/intel/fsp/fsp1_1/checklist" + endif #PLATFORM_USES_FSP1_1 diff --git a/src/vendorcode/intel/fsp/fsp1_1/checklist/bootblock_complete.dat b/src/vendorcode/intel/fsp/fsp1_1/checklist/bootblock_complete.dat new file mode 100644 index 0000000000..8a4325f4e0 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp1_1/checklist/bootblock_complete.dat @@ -0,0 +1,77 @@ +arch_segment_loaded +backup_top_of_ram +bootblock_mainboard_early_init +bootblock_mainboard_init +bootblock_soc_early_init +bootblock_soc_init +boot_device_init +car_mainboard_post_console_init +car_mainboard_pre_console_init +car_soc_post_console_init +car_soc_pre_console_init +cbfs_master_header_locator +cbmem_fail_resume +clear_recovery_mode_switch +cpu_smi_handler +fill_power_state +fw_cfg_acpi_tables +get_sw_write_protect_state +get_top_of_ram +gpio_acpi_path +init_timer +lb_board +lb_framebuffer +mainboard_add_dimm_info +mainboard_check_ec_image +mainboard_io_trap_handler +mainboard_memory_init_params +mainboard_post +mainboard_romstage_entry +mainboard_save_dimm_info +mainboard_silicon_init_params +mainboard_smi_apmc +mainboard_smi_gpi +mainboard_smi_sleep +mainboard_suspend_resume +map_oprom_vendev +mirror_payload +mrc_cache_get_current +mrc_cache_stash_data +northbridge_smi_handler +nvm_mmio_to_flash_offset +platform_prog_run +platform_segment_loaded +raminit +ramstage_cache_invalid +report_memory_config +save_chromeos_gpios +setup_stack_and_mtrrs +smbios_mainboard_bios_version +smbios_mainboard_manufacturer +smbios_mainboard_product_name +smbios_mainboard_serial_number +smbios_mainboard_set_uuid +smbios_mainboard_version +smm_disable_busmaster +soc_after_ram_init +soc_after_silicon_init +soc_display_memory_init_params +soc_display_silicon_init_params +soc_fill_acpi_wake +soc_memory_init_params +soc_pre_ram_init +soc_silicon_init_params +soc_skip_ucode_update +southbridge_smi_handler +stage_cache_add +stage_cache_load_stage +timestamp_get +timestamp_tick_freq_mhz +tsc_freq_mhz +vb2ex_hwcrypto_digest_extend +vb2ex_hwcrypto_digest_finalize +vb2ex_hwcrypto_digest_init +vboot_platform_prepare_reboot +verstage_mainboard_init +wifi_regulatory_domain +write_smp_table diff --git a/src/vendorcode/intel/fsp/fsp1_1/checklist/ramstage_complete.dat b/src/vendorcode/intel/fsp/fsp1_1/checklist/ramstage_complete.dat new file mode 100644 index 0000000000..64f8584340 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp1_1/checklist/ramstage_complete.dat @@ -0,0 +1,53 @@ +acpi_create_serialio_ssdt +arch_segment_loaded +backup_top_of_ram +boot_device_init +cbfs_master_header_locator +cbmem_fail_resume +clear_recovery_mode_switch +cpu_smi_handler +fw_cfg_acpi_tables +get_sw_write_protect_state +get_top_of_ram +gpio_acpi_path +init_timer +lb_board +lb_framebuffer +mainboard_add_dimm_info +mainboard_io_trap_handler +mainboard_post +mainboard_silicon_init_params +mainboard_smi_apmc +mainboard_smi_gpi +mainboard_smi_sleep +mainboard_suspend_resume +map_oprom_vendev +mirror_payload +northbridge_smi_handler +nvm_mmio_to_flash_offset +platform_prog_run +platform_segment_loaded +save_chromeos_gpios +smbios_mainboard_bios_version +smbios_mainboard_manufacturer +smbios_mainboard_product_name +smbios_mainboard_serial_number +smbios_mainboard_set_uuid +smbios_mainboard_version +smm_disable_busmaster +soc_after_silicon_init +soc_display_silicon_init_params +soc_fill_acpi_wake +soc_silicon_init_params +soc_skip_ucode_update +southbridge_smi_handler +stage_cache_add +stage_cache_load_stage +timestamp_get +timestamp_tick_freq_mhz +tsc_freq_mhz +vb2ex_hwcrypto_digest_extend +vb2ex_hwcrypto_digest_finalize +vb2ex_hwcrypto_digest_init +wifi_regulatory_domain +write_smp_table diff --git a/src/vendorcode/intel/fsp/fsp1_1/checklist/ramstage_optional.dat b/src/vendorcode/intel/fsp/fsp1_1/checklist/ramstage_optional.dat new file mode 100644 index 0000000000..6608583b28 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp1_1/checklist/ramstage_optional.dat @@ -0,0 +1,46 @@ +arch_segment_loaded +backup_top_of_ram +boot_device_init +cbmem_fail_resume +clear_recovery_mode_switch +cpu_smi_handler +fw_cfg_acpi_tables +get_sw_write_protect_state +get_top_of_ram +gpio_acpi_path +lb_board +lb_framebuffer +mainboard_add_dimm_info +mainboard_io_trap_handler +mainboard_post +mainboard_silicon_init_params +mainboard_smi_apmc +mainboard_smi_gpi +mainboard_smi_sleep +mainboard_suspend_resume +map_oprom_vendev +mirror_payload +northbridge_smi_handler +nvm_mmio_to_flash_offset +platform_prog_run +platform_segment_loaded +save_chromeos_gpios +smbios_mainboard_bios_version +smbios_mainboard_manufacturer +smbios_mainboard_product_name +smbios_mainboard_serial_number +smbios_mainboard_set_uuid +smbios_mainboard_version +smm_disable_busmaster +soc_after_silicon_init +soc_display_silicon_init_params +soc_silicon_init_params +soc_skip_ucode_update +southbridge_smi_handler +stage_cache_add +stage_cache_load_stage +vb2ex_hwcrypto_digest_extend +vb2ex_hwcrypto_digest_finalize +vb2ex_hwcrypto_digest_init +wifi_regulatory_domain +write_smp_table diff --git a/src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_complete.dat b/src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_complete.dat new file mode 100644 index 0000000000..e6bef6cf26 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_complete.dat @@ -0,0 +1,54 @@ +arch_segment_loaded +backup_top_of_ram +boot_device_init +cbfs_master_header_locator +cbmem_fail_resume +clear_recovery_mode_switch +cpu_smi_handler +fill_power_state +get_sw_write_protect_state +get_top_of_ram +gpio_acpi_path +init_timer +mainboard_add_dimm_info +mainboard_check_ec_image +mainboard_fill_spd_data +mainboard_io_trap_handler +mainboard_memory_init_params +mainboard_post +mainboard_romstage_entry +mainboard_save_dimm_info +mainboard_smi_apmc +mainboard_smi_gpi +mainboard_smi_sleep +map_oprom_vendev +migrate_power_state +mrc_cache_get_current_with_version +mrc_cache_stash_data_with_version +platform_prog_run +platform_segment_loaded +print_fsp_info +raminit +ramstage_cache_invalid +report_memory_config +romstage_common +save_chromeos_gpios +set_max_freq +setup_stack_and_mtrrs +smm_region +smm_region_size +soc_after_ram_init +soc_display_memory_init_params +soc_display_mtrrs +soc_get_variable_mtrr_count +soc_memory_init_params +soc_pre_ram_init +southbridge_smi_handler +stage_cache_add +stage_cache_load_stage +timestamp_get +tsc_freq_mhz +vb2ex_hwcrypto_digest_extend +vb2ex_hwcrypto_digest_finalize +vb2ex_hwcrypto_digest_init +vboot_platform_prepare_reboot diff --git a/src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_optional.dat b/src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_optional.dat new file mode 100644 index 0000000000..2634566528 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_optional.dat @@ -0,0 +1,34 @@ +arch_segment_loaded +backup_top_of_ram +boot_device_init +cbmem_fail_resume +clear_recovery_mode_switch +cpu_smi_handler +get_sw_write_protect_state +get_top_of_ram +gpio_acpi_path +mainboard_add_dimm_info +mainboard_check_ec_image +mainboard_io_trap_handler +mainboard_post +mainboard_romstage_entry +mainboard_save_dimm_info +mainboard_smi_apmc +mainboard_smi_gpi +mainboard_smi_sleep +map_oprom_vendev +platform_prog_run +platform_segment_loaded +save_chromeos_gpios +soc_after_ram_init +soc_display_memory_init_params +soc_display_mtrrs +soc_get_variable_mtrr_count +soc_memory_init_params +soc_pre_ram_init +southbridge_smi_handler +stage_cache_add +stage_cache_load_stage +vb2ex_hwcrypto_digest_extend +vb2ex_hwcrypto_digest_finalize +vb2ex_hwcrypto_digest_init diff --git a/src/vendorcode/intel/fsp/fsp1_1/checklist/verstage_complete.dat b/src/vendorcode/intel/fsp/fsp1_1/checklist/verstage_complete.dat new file mode 100644 index 0000000000..2124f0f2e5 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp1_1/checklist/verstage_complete.dat @@ -0,0 +1,35 @@ +arch_segment_loaded +backup_top_of_ram +boot_device_init +car_mainboard_post_console_init +car_mainboard_pre_console_init +car_soc_post_console_init +car_soc_pre_console_init +cbfs_master_header_locator +cbmem_fail_resume +clear_recovery_mode_switch +cpu_smi_handler +get_sw_write_protect_state +gpio_acpi_path +init_timer +mainboard_check_ec_image +mainboard_io_trap_handler +mainboard_post +mainboard_smi_apmc +mainboard_smi_gpi +mainboard_smi_sleep +map_oprom_vendev +platform_prog_run +platform_segment_loaded +save_chromeos_gpios +soc_display_mtrrs +soc_get_variable_mtrr_count +stage_cache_add +stage_cache_load_stage +timestamp_get +tsc_freq_mhz +vb2ex_hwcrypto_digest_extend +vb2ex_hwcrypto_digest_finalize +vb2ex_hwcrypto_digest_init +vboot_platform_prepare_reboot +verstage_mainboard_init diff --git a/src/vendorcode/intel/fsp/fsp1_1/checklist/verstage_optional.dat b/src/vendorcode/intel/fsp/fsp1_1/checklist/verstage_optional.dat new file mode 100644 index 0000000000..f589eaa919 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp1_1/checklist/verstage_optional.dat @@ -0,0 +1,22 @@ +arch_segment_loaded +backup_top_of_ram +boot_device_init +car_mainboard_post_console_init +car_mainboard_pre_console_init +car_soc_post_console_init +car_soc_pre_console_init +mainboard_check_ec_image +mainboard_post +platform_prog_run +platform_segment_loaded +soc_display_mtrrs +soc_get_variable_mtrr_count +stage_cache_add +stage_cache_load_stage +timestamp_get +tsc_freq_mhz +vb2ex_hwcrypto_digest_extend +vb2ex_hwcrypto_digest_finalize +vb2ex_hwcrypto_digest_init +vboot_platform_prepare_reboot +verstage_mainboard_init -- cgit v1.2.3