From fac2893584514afb1d64e71167a8564d1da26c26 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sun, 3 May 2020 08:30:09 +0200 Subject: soc/intel/broadwell/adsp: Fix 8-bit write on PCI_INTERRUPT_LINE register The PCI_INTERRUPT_LINE register is one byte wide. Possible side effects of clearing the three bytes after PCI_INTERRUPT_LINE are unknown. Change-Id: I64e785309b0bf7f4d74436ea12a2444092deae22 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/41009 Reviewed-by: Angel Pons Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/soc/intel/broadwell/adsp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/soc/intel/broadwell/adsp.c b/src/soc/intel/broadwell/adsp.c index 27368c0518..897f9c4ee3 100644 --- a/src/soc/intel/broadwell/adsp.c +++ b/src/soc/intel/broadwell/adsp.c @@ -115,7 +115,7 @@ static void adsp_init(struct device *dev) printk(BIOS_INFO, "ADSP: Enable PCI Mode IRQ23\n"); /* Configure for PCI mode */ - pci_write_config32(dev, PCI_INTERRUPT_LINE, ADSP_PCI_IRQ); + pci_write_config8(dev, PCI_INTERRUPT_LINE, ADSP_PCI_IRQ); /* Clear ACPI Interrupt Enable Bit */ pch_iobp_update(ADSP_IOBP_PCICFGCTL, -- cgit v1.2.3